Intel Says Backside Power Gives It an Edge in High NA EUV Chip Manufacturing
Intel is making a bold case for why its next-generation manufacturing strategy could give it an advantage in the race for advanced semiconductor production. According to Chris Auth, Intel’s vice president and general manager for manufacturing development and customer engagement, the company’s use of backside power delivery may allow it to take better advantage of High NA EUV lithography than TSMC.
Auth shared the comments during a recent technology-focused podcast discussion, where Intel executives outlined how the company plans to compete in leading-edge chip manufacturing. The core argument is simple: Intel’s architecture may reduce some of the most difficult front-side wiring constraints, making it easier to use High NA EUV tools efficiently.
High NA EUV lithography is one of the most important technologies for the future of chip fabrication. These advanced machines improve the resolution of light used to print tiny circuit patterns on silicon wafers. That matters because modern processors require extremely dense and precise features, and every new generation pushes those patterns closer together.
In semiconductor manufacturing, “pitch” refers to the spacing between two features on a chip. Smaller pitches allow greater transistor density, but they also make manufacturing much harder. If the spacing is too tight, chipmakers often need to use multiple patterning steps, which increases cost, complexity, and production time.
Auth explained that Intel’s backside power delivery helps ease some of those pitch requirements on the front side of the chip. By moving power delivery circuitry to the back of the wafer, Intel can free up more room on the front side for logic transistors and signal interconnects. This, according to Auth, allows Intel to print certain structures more directly with High NA EUV.
He said Intel’s use of backside power “alleviates some of the pitch requirements” on the front side, enabling the company to use High NA EUV in a more straightforward way. In contrast, he suggested that TSMC faces tighter pitch demands because it does not yet use backside power in the same way, which can require additional EUV patterning steps.
That distinction could become important as Intel pushes its 14A process technology. Auth noted that 14A is already available as an option in the company’s process design kit, with adoption being handled through customer-by-customer discussions.
Intel’s backside power technology is one of the company’s most important bets in advanced chip manufacturing. Traditionally, both power delivery and signal routing are handled from the front side of the wafer. But as chips become denser, routing power through the same side as the transistors can create congestion and reduce efficiency.
By shifting power delivery to the back of the silicon, Intel aims to improve power efficiency, reduce resistance, and create more space for performance-critical circuitry. This design approach is expected to become increasingly important as the industry moves toward smaller process nodes and more complex transistor structures.
The discussion also touched on Intel’s broader effort to compete with TSMC in the global foundry market. Intel chief technology officer Pushkar Ranade acknowledged that TSMC remains a much larger wafer manufacturer today. He said catching up in production scale will take time and will happen gradually.
However, Ranade argued that the technology gap is no longer the main issue. In his view, Intel is already competitive in leading-edge process technology, even if there may be small differences in performance, power, or area density.
He emphasized that the real challenge is execution. Being a few percentage points ahead or behind in one metric is less important than delivering on time, achieving strong yields, and ramping production quickly.
Ranade’s point highlights one of the biggest realities of the semiconductor industry: advanced technology is only valuable if it can be manufactured reliably at scale. A process node must not only deliver strong performance on paper, but also support high-volume production with consistent yields.
For Intel, that means proving that its manufacturing roadmap can meet customer expectations. The company has repeatedly expressed confidence in its 14A process, while the broader semiconductor industry continues to move aggressively toward next-generation nodes.
The conversation also addressed future transistor designs, including the industry’s push toward stacking n-type and p-type transistors. These two transistor types are fundamental to modern chip design, and stacking them is viewed as a potential path toward even denser and more efficient chips.
This concept is often discussed in connection with complementary field-effect transistors, or CFETs, which could represent a major step beyond today’s gate-all-around transistor designs. By stacking transistor types vertically, chipmakers may be able to reduce footprint and improve density.
But Intel’s Jack Kavalieros, vice president of components research and an Intel Fellow, warned that stacking transistors introduces major manufacturing challenges. He explained that connections that were once placed on the top or bottom of a structure may need to run vertically between transistors.
That creates new difficulties in forming and filling extremely narrow trenches. As the aspect ratios become more extreme, it becomes harder to fill those spaces properly. If the process is not controlled precisely, air gaps or voids can form, potentially affecting reliability and performance.
In other words, the future of chipmaking is not just about stacking more components or shrinking dimensions. It is also about solving the complex interconnect, materials, and manufacturing problems that come with these new structures.
Intel’s message is clear: the company believes its combination of backside power delivery, High NA EUV readiness, and advanced process development can help it regain momentum in semiconductor manufacturing. But the path forward will depend on more than technical ambition. It will require precise execution, strong yields, customer confidence, and the ability to scale production on schedule.
As competition intensifies in the foundry market, Intel’s 14A process could become a critical test of the company’s comeback strategy. If Intel can deliver on its promises, backside power and High NA EUV may play a major role in shaping the next era of advanced processors.
