ASML’s High-NA EUV Roadmap Could Shape the Next Decade of AI Chips
ASML has become one of the most important companies in the semiconductor world because it controls a technology that the entire advanced chip industry depends on: EUV lithography. As demand for AI processors, accelerators, and high-performance computing hardware continues to surge, the ability to manufacture chips on the most advanced process nodes is becoming one of the biggest constraints in the global technology supply chain.
The AI boom is not limited by one factor alone. Power, packaging, memory, networking, cooling, data centers, and materials all play a role. But at the heart of the entire stack is still the chip itself. And for cutting-edge semiconductors, especially those built on sub-7nm process nodes, EUV lithography capacity remains a critical bottleneck.
Why EUV capacity matters for AI chip production
Modern AI chips require extremely dense transistor layouts, and that level of precision is only possible with EUV lithography. Foundries can improve output by increasing tool uptime, optimizing workflows, and pushing utilization higher, but there is a hard limit. EUV machines are incredibly complex, expensive, and produced in limited numbers each year.
That means every major chipmaker and foundry is competing for access to the same class of tools. As hyperscalers continue to expand AI infrastructure at an aggressive pace, the pressure on leading-edge wafer production is only getting stronger.
This is why ASML’s next-generation EUV systems are so important. The company has been preparing High-NA EUV as the next major step in lithography, designed to simplify advanced chip production and help foundries continue shrinking process nodes.
High-NA EUV moves closer to high-volume manufacturing
Traditional EUV systems use 0.33 numerical aperture, often referred to as Low-NA EUV. ASML’s High-NA EUV moves that figure to 0.55, allowing chipmakers to print smaller features with fewer exposure steps.
That matters because multiple patterning adds complexity, cost, time, and energy consumption. With High-NA EUV, certain lithography processes that previously required three exposures may be reduced to just one. The mask process can also see a similar reduction in steps, making advanced chip manufacturing more efficient.
ASML shipped its first 0.55 NA EUV lithography system, the EXE:5000, in the fourth quarter of 2023. The first wafer exposure on that machine took place in the third quarter of 2024. The EXE:5000 is capable of processing around 110 wafers per hour.
Its successor, the EXE:5200B, reached customers in the fourth quarter of 2025. With the help of a 1000W laser source, this newer system can reach up to 175 wafers per hour, marking a major improvement in throughput.
High-NA EUV has also reached an important production milestone, with 500,000 High-NA wafers achieved by December 2025. That progress suggests the technology is moving steadily toward high-volume manufacturing as customers continue qualification work.
For the semiconductor industry, this is a major development. High-NA EUV is not just a technical upgrade; it is a key enabler for the next wave of advanced processors, AI accelerators, and high-performance computing chips.
What comes after High-NA EUV?
ASML is already looking beyond High-NA. The next stage is known as Hyper-NA EUV, which refers to systems with a numerical aperture above 0.75.
Hyper-NA is expected to support further scaling beyond the A7 node, which is projected to enter high-volume manufacturing around 2033. If the industry wants to keep single-exposure EUV lithography practical into the second half of the 2030s, another jump in numerical aperture will likely be needed.
The good news is that Hyper-NA may not require a dramatic increase in optical system size compared with High-NA. That could allow ASML to reuse the High Performance Platform introduced with the EXE generation of machines, helping reduce the complexity of the transition.
Why Hyper-NA could be important for future chips
The main benefit of increasing numerical aperture is straightforward: smaller features can be printed with fewer patterning steps. This helps preserve single-exposure lithography for future process nodes and reduces the need for increasingly complicated multi-patterning techniques.
Fewer mask steps can also reduce energy consumption during manufacturing. That is becoming more important as chip production grows more expensive and power-intensive. Although Hyper-NA tools will likely cost more than current High-NA systems, the long-term efficiency improvements could make them essential for future semiconductor scaling.
The future of EUV is tied to the future of semiconductors
ASML’s High-NA and Hyper-NA roadmap shows how the semiconductor industry plans to keep advancing despite mounting technical challenges. AI demand is pushing foundries to produce more cutting-edge wafers than ever, but that growth depends on the availability and performance of EUV lithography systems.
High-NA EUV is now approaching the stage where it can move from early adoption and qualification into broader high-volume manufacturing. Hyper-NA EUV, meanwhile, is already being positioned as the next major leap for the 2030s.
As AI chips become larger, denser, and more powerful, lithography will remain one of the most important technologies behind the scenes. The companies that can secure advanced EUV capacity will have a major advantage in the next generation of semiconductor manufacturing.
