China’s chip industry may have found a new way to push older DUV lithography tools much further than expected. While export restrictions continue to limit access to the most advanced EUV equipment, researchers at the Chinese Academy of Sciences have reportedly developed a new gate-all-around transistor design that could help deliver performance approaching advanced 3nm-class chips in certain areas.
The breakthrough centers on GAA transistors, a more advanced transistor structure that offers tighter control over electrical current than traditional FinFET designs. In simple terms, transistors act like tiny switches inside a processor, rapidly turning current on and off to represent the 1s and 0s used in computing. Modern chips contain billions of these switches, so improving their efficiency, density, and power control can have a major impact on performance.
FinFET transistors use a fin-like structure, where the gate controls the channel from multiple sides. GAA transistors go further by surrounding the channel more completely, giving the gate better control over current flow. A useful comparison is gripping a hose with your whole hand instead of pinching it with two fingers. This stronger control can reduce leakage, improve efficiency, and allow chip designers to rethink how densely components need to be packed.
According to the reported development, the Chinese Academy of Sciences has created GAA transistors with on-off ratios above 500,000. That means the current flowing when the transistor is switched on is more than 500,000 times greater than the current leaking through when it is off. This is an important indicator of strong electrical control and low leakage, both of which are essential for advanced semiconductor manufacturing.
What makes the development especially notable is the claim that these transistors can be produced using DUV lithography machines. Deep ultraviolet lithography is older than EUV and is generally not considered ideal for printing the extremely fine patterns required for cutting-edge 3nm-class chips. However, manufacturers can extend DUV capabilities through techniques such as multi-patterning, where the same layer is exposed and etched in multiple steps to create finer features. Immersion DUV, which uses ultra-pure water to improve optical resolution, can also help push older equipment closer to advanced manufacturing limits.
China has already used these methods to produce competitive chips despite equipment restrictions. The latest GAA transistor research suggests there may be another route forward: instead of relying only on shrinking every part of the chip, manufacturers may improve transistor behavior enough to achieve performance that resembles more advanced nodes.
However, this does not mean China has fully replicated a true 3nm manufacturing process. Semiconductor production involves several major stages, and the transistor itself is only one part of the equation.
The front-end-of-line stage, known as FEOL, is where the transistors are created. This is where the new GAA design could provide a major advantage. Because GAA transistors offer better electrical control, chipmakers may be able to loosen the fin pitch, meaning transistors would not need to be packed as tightly as older FinFET designs to deliver similar performance.
The middle-end-of-line stage, or MEOL, is more complicated. This part of the process connects the transistors to the rest of the circuit through extremely small trenches, holes, and contacts filled with metal. The back-end-of-line stage, known as BEOL, handles the wider network of metal wiring layers that connect different areas of the chip. One of the most difficult layers is M0, the lowest metal layer, because it sits closest to the transistors and requires extremely fine patterning.
These wiring and contact layers remain a major challenge for companies such as SMIC. Improvements to GAA transistor design do not automatically solve the difficulty of manufacturing precise MEOL contacts or the finest BEOL metal layers. Even poly pitch, which refers to the spacing between transistor gates, can be limited by MEOL complexity.
Still, the new transistor architecture could create a practical advantage. If the fin pitch can be relaxed thanks to better GAA control, SMIC may be able to reduce logic cell height by moving from a 5-track M0 design to a 4-track version. That could enable cell structures with densities around 137.8 million transistors per square millimeter, placing them in a class comparable to leading 5nm logic density.
In other words, the breakthrough may not instantly deliver full 3nm manufacturing, but it could help Chinese chipmakers achieve 5nm-class density and 3nm-like performance characteristics in selected areas, using equipment that is still available to them. That would be a meaningful step for China’s semiconductor ambitions.
This strategy also fits into a broader pattern. Huawei and SMIC are not relying on one single solution to overcome lithography limits. Instead, they appear to be combining process improvements, transistor architecture changes, chip packaging, and design-level innovations.
Huawei, for example, has been linked to next-generation Ascend 960 AI chips that may use a technique called LogicFolding. This approach stacks logic circuits vertically to increase compute density even when individual transistor density is limited. By building upward rather than only shrinking sideways, chip designers can shorten signal paths and improve efficiency. Fine-pitch vertical interconnects allow different silicon layers to work together almost like one unified chip.
This is especially important for artificial intelligence processors, where compute density, memory bandwidth, power efficiency, and interconnect speed all matter. If traditional scaling becomes harder due to equipment restrictions, vertical integration and advanced packaging can help compensate.
The bigger picture is clear: China’s semiconductor industry is trying to extract maximum value from DUV lithography while developing alternative paths to advanced chip performance. The Chinese Academy of Sciences’ GAA transistor work could become a key part of that effort, particularly if it can be translated from research into mass production.
There are still major obstacles. Manufacturing advanced chips at high yield is far more difficult than demonstrating a promising transistor design. MEOL and BEOL limitations remain serious bottlenecks, and DUV multi-patterning can be expensive, complex, and time-consuming. But the progress suggests that older lithography tools may have more room left than many expected.
If CAS, SMIC, Huawei, and other players can combine GAA transistors with improved DUV patterning, tighter process control, vertical logic stacking, and better packaging, China could continue narrowing the gap in advanced semiconductor performance even without access to the most advanced lithography machines.
For now, the development should be viewed as a promising pathway rather than a finished 3nm replacement. But in the global race for semiconductor independence, even a partial workaround can be highly significant.
