TSMC sets sights on 2nm mass production in late 2025 as wafer prices hit $30,000
Taiwan Semiconductor Manufacturing Company plans to kick off volume production of its 2nm chips in the fourth quarter of 2025, even as advanced-node wafer pricing climbs to an unprecedented US$30,000 per wafer. The move underscores TSMC’s confidence in ramping its next-generation process technology on schedule while navigating the higher costs that come with cutting-edge manufacturing.
The 2nm generation is expected to usher in a new architecture shift to nanosheet gate-all-around transistors, enabling meaningful gains in performance and energy efficiency over the current 3nm family. Those improvements are especially attractive for power-sensitive mobile devices and performance-hungry data center silicon, including AI accelerators, CPUs, and GPUs.
Why the price tag is soaring
– More extreme ultraviolet (EUV) layers and complex process steps add significant cost.
– Early-stage yields at a brand-new node typically start lower, raising effective wafer costs during the initial ramp.
– Massive capital expenditures on new equipment and cleanroom space must be amortized across each wafer.
– Transitioning to a new transistor architecture requires additional process development and tighter controls.
What it means for the market
– Leading-edge customers with the most demanding performance-per-watt targets are likely to be first in line, absorbing higher costs to secure competitive advantages.
– Premium smartphones, high‑end laptops, and cloud/AI infrastructure are the most probable early beneficiaries of 2nm’s efficiency gains.
– Chip pricing at the top end may remain elevated, with mainstream products continuing to rely on mature 3nm and 5nm-class nodes for cost efficiency.
– Expect a gradual ramp: early volumes will be constrained as yields improve and capacity scales through 2026.
The bottom line
Despite record-high wafer pricing, TSMC’s plan to begin volume production of 2nm chips in Q4 2025 signals a steady march to the next milestone in semiconductor performance and efficiency. As the node ramps, the most advanced devices should see notable gains, while broader adoption will follow as yields rise and costs normalize.
