TSMC is gearing up for its next big leap in semiconductor manufacturing with A16, a 1.6nm-class process that signals the beginning of what the company calls its “Angstrom Era.” The key promise is simple but significant: better performance and power efficiency than its 2nm generation, along with a major upgrade in how chips receive power.
TSMC is expected to formally showcase A16 at the 2026 VLSI symposium, positioning it as a core member of a new advanced-node family that also includes A14 and the recently outlined A13 and A12. While node naming can be confusing, the story here is straightforward: A16 is designed to push higher speeds, reduce energy use, and improve density—especially for demanding products like high-performance computing and AI accelerators.
The standout feature for A16 is backside power delivery, a design shift where the chip’s power rails move to the back side of the wafer. TSMC’s implementation is branded as Super Power Rail (SPR). Why does that matter? By relocating power delivery away from the front side, more front-side routing resources can be dedicated to signals. In practice, that can help chips handle dense, complex wiring more efficiently while also improving power integrity—one of the biggest headaches in modern high-transistor designs.
A16 also builds on an optimized nanosheet transistor approach, following the nanosheet technology introduced with TSMC’s 2nm generation. Nanosheet transistors are a major evolution beyond FinFET, giving chip designers more flexibility and better control at tiny geometries—an important foundation for scaling into the 1.x nm era.
In terms of expected gains, TSMC indicates that A16 can deliver:
– An 8–10% speed increase versus N2P at the same core area
– Roughly 15–20% lower power at the same performance level
– Up to about 1.10x chip density, with cited improvements in logic and SRAM density in the 8–10% range
TSMC specifically frames A16 as a strong fit for high-performance computing chips that need both complex signal routing and heavy, stable power delivery—exactly the kind of designs used in modern AI infrastructure.
As for timing, A16 is currently targeted for mass production in Q4 2026. That said, “mass production” doesn’t always mean you’ll immediately see products on shelves. Real-world chips built on A16 are more likely to show up around 2027 to 2028, based on typical development and product cycles.
TSMC’s Angstrom roadmap doesn’t stop at A16. The company is also lining up:
– A14 (1.4nm), a key stepping-stone node expected to enter production before A13
– A13 (1.3nm), described as a shrink of A14 with around 6% area savings and full backward compatibility with A14, aimed at HPC, AI, and mobile devices, and planned for production around 2029
– A12 (1.2nm), another evolution tied to A14 that also uses Super Power Rail backside power delivery, likewise targeted for around 2029
All of these nodes arrive at a time when semiconductor manufacturing capacity is under intense pressure, driven largely by continued AI demand. As TSMC expands output across its fabs and brings new facilities online, the competitive landscape is also shifting. Rivals are pushing advanced packaging and new leading-edge process offerings in an attempt to capture customers who need cutting-edge performance but face supply constraints.
The bottom line: TSMC’s A16 isn’t just a smaller node—it’s a platform change. By combining nanosheet transistors with backside power delivery through Super Power Rail, TSMC is aiming to improve speed, efficiency, and density in the kinds of chips that will define the next wave of AI and high-performance computing hardware.
