TSMC has laid out its semiconductor technology roadmap through 2029, offering a clearer look at the company’s next wave of chipmaking processes and advanced packaging innovations. The big takeaway: TSMC plans to keep pushing performance and efficiency forward with refined node shrinks like A13 and A12, while continuing to rely on its current EUV toolset rather than moving to ASML’s newest High-NA EUV machines—at least for now.
TSMC’s process timeline starts with N2 (2nm), which is expected to reach mass production with the first products arriving this year. From there, the roadmap rolls into a steady cadence of updates and extensions: N2P and N3A are targeted for 2026, followed by N2X and A16 in 2027, then A14 and N2U in 2028. By 2029, the company plans to introduce A13 and A12, two new advanced nodes designed to further refine the A14 generation.
TSMC is also balancing cutting-edge node development with “mainstream-optimized” options aimed at broader product coverage. For example, N3C is expected in 2026, and N2U is positioned to serve both high-end and mainstream needs, depending on the customer’s performance, power, and cost targets.
A closer look at A13 (1.3nm): a tighter, more efficient A14 shrink
TSMC previewed its A13 process as a direct shrink of A14 (1.4nm). The headline improvement here is a 6% area savings versus A14, enabling more compact chip designs—an especially important benefit in high-performance computing, AI accelerators, and next-generation mobile chips where maximizing compute per square millimeter can strongly influence cost and scalability.
Beyond die shrink, A13 is designed to be fully backward compatible with A14, which can reduce transition friction for chip designers and potentially shorten development timelines. Production is currently slated for 2029, following A14 by roughly a year.
A12 (1.2nm) adds backside power with Super Power Rail
TSMC’s A12 (1.2nm) is another A14-derived enhancement planned for 2029, but with a key technology addition: Super Power Rail for backside power delivery. Backside power is a major industry shift because it helps separate power routing from signal routing, improving efficiency and reducing congestion in increasingly complex designs. In practice, that can help improve performance-per-watt and make it easier to scale demanding chips as densities rise.
N2U (2nm) aims to be a mature, balanced option for AI, HPC, and mobile
On the N2 platform, TSMC is introducing N2U, a new node described as a more balanced and mature evolution of N2. According to the details shared, N2U targets either a 2–4% speed improvement or an 8–10% power reduction at the same performance. Logic density is also expected to rise modestly—about 1.02–1.03x versus N2P.
Importantly, N2U is presented as a node that benefits from maturity and yield improvements because it builds on the N2 foundation. It’s currently expected to be ready for production in 2028, making it a key stepping stone between the first wave of 2nm products and the A14/A13 era.
Advanced packaging gets bigger, denser, and more ambitious
While smaller process nodes often grab the spotlight, TSMC’s roadmap also underscores how crucial advanced packaging has become—especially for AI and data center workloads where multi-die designs, massive memory bandwidth, and faster chip-to-chip communication matter as much as the transistor node.
TSMC highlighted work across several packaging directions, including 3D silicon stacking and 3D fabric technologies. The company’s widely used CoWoS (Chip-on-Wafer-on-Silicon) packaging is also scaling up significantly. TSMC says CoWoS can now support 5.5-reticle-sized products, with larger designs on the way. A 14-reticle CoWoS solution is planned for 2028, with the ability to integrate up to 10 compute dies and 20 HBM stacks—an eye-catching configuration for next-gen AI accelerators. Looking further out, TSMC targets a 40-reticle SoW-X capability in 2029, signaling continued momentum toward ever-larger, higher-integration compute platforms.
TSMC is also expanding its SoIC 3D chip stacking on advanced nodes. A14-to-A14 SoIC is expected to be available for production in 2029, delivering a claimed 1.8x higher die-to-die I/O density compared with N2-on-N2 SoIC. Higher I/O density is critical for boosting bandwidth between stacked components, helping multi-die architectures act more like a single, tightly integrated chip.
Co-packaged optics moves closer to production
Another notable milestone is TSMC’s Compact Universal Photonic Engine (COUPE), which is expected to reach a key stage with a true co-packaged optics solution—COUPE on substrate—beginning production in 2026. By moving the optical engine directly into the package, TSMC claims 2x power efficiency and 10x latency reduction compared with a pluggable optics approach on the circuit board. The company highlighted a 200Gbps micro-ring modulator implementation aimed at compact, energy-efficient high-speed data movement between racks in data centers.
Why TSMC plans to wait on ASML High-NA EUV through 2029
Alongside the technical roadmap, TSMC made it clear it intends to hold off on adopting ASML’s advanced High-NA EUV lithography tools through 2029. The company’s position isn’t that High-NA lacks value, but that current EUV remains capable of delivering meaningful scaling and improvements—particularly for A14 and its follow-on shrinks—without taking on the significant cost burden of next-generation lithography equipment.
TSMC leadership indicated the company will adopt High-NA when it delivers a “meaningful, measurable benefit,” but for now the strategy is to extend the life of existing EUV systems while continuing to harvest scaling gains. With the AI boom driving massive investment in new fabs and capacity expansion, the economics of adding extremely expensive next-gen lithography tools appear to be a major consideration. In the meantime, TSMC will focus on process optimizations and die shrinks such as A13 and A12, paired with aggressive packaging innovation to keep performance climbing.
What this means for future chips
TSMC’s 2029 roadmap signals a dual-track future for cutting-edge computing: continued transistor scaling through refined nodes like A14, A13, and A12, plus rapid advances in packaging that enable larger “virtual chips,” higher HBM integration, faster chip-to-chip links, and even optical connectivity inside the package. For AI, HPC, and premium mobile devices, these developments point to more performance per watt, denser designs, and new ways to scale compute beyond the limits of a single monolithic die.
