China’s Naura Technology Group claims progress in 3D DRAM manufacturing with new etch process
China’s push to strengthen its domestic semiconductor industry may have taken another step forward. Naura Technology Group, one of the country’s important chipmaking equipment suppliers, says it has developed a two-step etching process that could support the production of next-generation 3D DRAM memory chips.
3D DRAM is viewed as a major evolution in memory technology because it aims to solve one of the biggest challenges facing conventional DRAM: increasing cell density without relying only on shrinking horizontal circuit patterns. Instead of spreading components across a flat silicon surface, 3D DRAM stacks structures vertically, allowing more memory capacity in a smaller footprint.
According to research published by Naura in an IEEE journal, the company has made progress in achieving uniform etching across a 64-layer 3D DRAM structure. If scalable, this kind of process could become important for Chinese memory manufacturers working to advance chip production despite limited access to the world’s most advanced lithography systems.
Why vertical chip design matters for China
Advanced EUV lithography machines are heavily restricted for Chinese companies due to export controls. These machines are critical for producing the most advanced chips because they allow manufacturers to print extremely tiny circuit patterns across silicon wafers.
Without easy access to EUV tools, Chinese semiconductor firms have been exploring alternative methods to improve chip density and performance. One major strategy is vertical scaling, where chip structures are stacked upward rather than only made smaller horizontally.
This approach has already gained attention in logic chip design. Earlier this year, Huawei discussed a technology known as Tau Scaling, which includes a LogicFolding architecture designed to fold and stack logic circuits vertically. The goal is to reduce resistance, improve connections, and increase transistor density without depending entirely on smaller lithography nodes.
Naura’s newly detailed work suggests that a similar direction may be emerging in memory manufacturing, particularly for 3D DRAM.
How Naura’s 3D DRAM etching process works
In 3D DRAM structures, layers of silicon and silicon-germanium are stacked alternately. During production, the silicon-germanium layers must be selectively removed while leaving the silicon layers largely intact. This creates the necessary spaces for key memory components such as word lines, bit lines, and gates.
This removal process is called etching. However, etching at high layer counts is extremely difficult. The chemicals used to remove silicon-germanium can damage nearby silicon layers, process by-products can build up near the bottom of the structure, and etching performance can become uneven as the chemicals struggle to reach deeper layers.
These issues can reduce chip quality and make mass production more difficult. In semiconductor engineering, two of the biggest problems are low selectivity and micro-loading. Low selectivity means the etching process does not cleanly distinguish between the target material and the material that must be preserved. Micro-loading refers to uneven etching or residue buildup, especially in deeper parts of the structure.
Naura says its two-step process is designed to solve both problems.
The first step uses electrically neutral fluorine radicals to target the silicon-germanium layers. Because the radicals are unbiased, they can remove silicon-germanium while reducing unwanted damage to the surrounding silicon. During this stage, a thin protective germanium fluoride film forms on the silicon surface, helping shield it from further damage.
The second step uses a plasma-assisted purge to clear away chemical by-products. This helps reduce micro-loading and improves etching consistency from the top of the structure down to the bottom.
The company claims this process can achieve silicon-to-silicon-germanium etch selectivity of more than 500 to 1. In simpler terms, the silicon-germanium layer is removed more than 500 times faster than the silicon layer, allowing the target material to be etched away while preserving the surrounding structure.
Naura also claims silicon loss is less than 10 angstroms, which is extremely small. In addition, the company says it achieved structural uniformity above 95% across 64 layer pairs. That means if the top layer opening is 200 nanometers thick, the bottom layer remains at least about 190 nanometers thick, showing strong consistency throughout the stacked structure.
Why this could matter for future DRAM production
If Naura’s process can be applied in commercial manufacturing, it could help Chinese memory companies develop more advanced 3D DRAM products. This would be especially relevant for firms such as CXMT, which is working to compete in the memory market while navigating restrictions on advanced chipmaking equipment.
The breakthrough is not the same as having access to EUV lithography, and it does not automatically mean China can immediately produce world-leading DRAM. However, it highlights a broader shift in semiconductor development: when horizontal scaling becomes harder, chipmakers look upward.
For memory chips, vertical stacking could become increasingly important as traditional planar DRAM approaches physical and economic limits. A reliable high-selectivity etching method is one of the key building blocks needed to make dense 3D memory structures practical.
Naura’s research shows that Chinese semiconductor equipment makers are focusing on the complex manufacturing steps required for advanced vertical chip architectures. Etching may not receive as much public attention as lithography, but it is just as essential in building modern semiconductors.
The road ahead for 3D DRAM
3D DRAM is still a challenging technology. Producing it at scale requires precise deposition, patterning, etching, cleaning, inspection, and process control across many layers. Even small defects can affect yield and performance.
Still, Naura’s reported results suggest meaningful progress in one of the hardest parts of the process: selectively removing silicon-germanium across a deep multilayer stack while preserving silicon uniformity.
As the global memory industry searches for new ways to increase density and performance, 3D DRAM is expected to become an increasingly important area of research. For China, advances in vertical memory fabrication could provide a path to continue improving chip capabilities despite limits on access to cutting-edge lithography tools.
Naura’s two-step etch process may therefore represent more than a technical milestone. It could be part of a larger strategy to build a more self-reliant semiconductor supply chain and develop advanced memory manufacturing methods suited to the constraints and opportunities facing China’s chip industry.
