Intel Diamond Rapids Xeon 7 CPUs Aim for 256 P-Cores, PCIe 6.0, and Massive AI Data Center Performance
Intel is preparing one of its most ambitious data center CPU upgrades yet with Diamond Rapids, the next-generation Xeon 7 platform designed to handle the growing demands of enterprise AI, cloud infrastructure, and high-performance computing. Built on Intel’s enhanced 18A-P process technology, Diamond Rapids is expected to bring up to 256 performance cores, a major jump in memory bandwidth, faster I/O, and a new architecture aimed at large-scale agentic AI workloads.
The new chips will arrive after Intel’s current and upcoming data center platforms, including Granite Rapids and Clearwater Forest. While those products already mark important steps for Intel’s server roadmap, Diamond Rapids appears to be a much larger architectural shift. Intel is positioning the CPU family as a versatile enterprise processor that can scale across AI, cloud, database, analytics, virtualization, and infrastructure-as-a-service environments.
A major highlight of Diamond Rapids is its use of Intel 18A-P, an enhanced version of the Intel 18A process. Intel has already placed significant focus on 18A for products such as Panther Lake in client systems and Clearwater Forest in data centers. With 18A-P, the company is pushing further with improvements focused on power efficiency, performance, and scalable chip construction.
Diamond Rapids will power Intel’s Xeon 7 data center CPU family and introduce a new system-on-chip design built around disaggregated tiles. Instead of relying on one large monolithic chip, Intel is using multiple chiplets and fabric hubs connected through advanced packaging technologies. This approach allows Intel to scale core counts, memory access, and I/O capabilities more effectively for demanding enterprise workloads.
According to Intel’s early disclosures, Diamond Rapids uses a fan-out fabric architecture built around several key blocks: scalable compute building blocks, centralized I/O and memory through fabric hubs, a unified memory fabric, and flexible I/O fabric. The goal is to deliver strong and consistent performance while keeping memory latency uniform across the processor.
The chip design is expected to include 16 core chiplets built on Intel 18A-P, two fabric hubs built on Intel 3, four base tiles using Intel 3-T, and advanced hybrid bonding through Foveros Direct 3D. Intel is also using UCIe-S-based die-to-die interconnects through substrate copper links. Together, these technologies allow the company to pack far more compute and connectivity into a single server CPU package.
One of the biggest changes comes from Intel’s new Core Building Block design. Each compute chiplet includes 16 cores and connects to the shared last-level cache through a 3D crossbar. Unlike Granite Rapids, where the integrated memory controller sits closer to the compute tile, Diamond Rapids separates compute from the memory and I/O fabric. This gives Intel more flexibility in scaling compute chiplets and memory resources independently.
The full Diamond Rapids design can scale up to 256 P-Cores. That is a 50% increase over the 128-core ceiling of Granite Rapids Xeon 6 and places Intel directly in competition with high-core-count server processors from AMD. These cores are based on the Panther Cove-X architecture, a performance-core design optimized for high per-thread performance, cloud workloads, and enterprise infrastructure.
However, Diamond Rapids will not support simultaneous multithreading. That means the maximum thread count is expected to match the core count at 256 threads. Intel is expected to bring SMT support back with the successor to Diamond Rapids, currently known as Coral Rapids, which is planned for a later launch window.
Cache capacity is another major part of the Diamond Rapids story. The platform is expected to offer up to 1.28 GB of shared last-level cache across the chip. This massive cache pool should help reduce data movement and improve performance in workloads that are sensitive to memory access, including AI inference, large-scale databases, simulation, analytics, and virtualized cloud deployments.
Memory bandwidth is also being upgraded significantly. Diamond Rapids is expected to support a 16-channel memory design, giving servers much more bandwidth than current platforms. Intel has discussed support for faster DDR5 memory as well as MRDIMMs reaching speeds up to 12,800 MT/s. Standard DDR5 speeds may reach up to 8,000 MT/s depending on platform configuration. This will be especially important for bandwidth-limited applications, where CPU cores can sit idle if data cannot be delivered quickly enough.
The unified memory fabric inside Diamond Rapids is designed to handle up to 1.6 TB/s of memory bandwidth. It includes memory controllers, DDR PHYs, home agents, snoop filters, memory encryption, and memory interconnect components. Intel’s focus here is not just higher bandwidth, but also more predictable memory behavior across the chip, which matters greatly in large multi-socket systems and AI-driven enterprise workloads.
On the I/O side, Diamond Rapids is set to support up to 128 lanes of PCIe 6.0 along with CXL 3.0. That combination should make the platform highly attractive for servers packed with GPUs, AI accelerators, high-speed networking cards, storage devices, and memory expansion hardware. PCIe 6.0 doubles the bandwidth of PCIe 5.0, while CXL 3.0 opens the door for more advanced memory pooling, cache coherency, and composable infrastructure.
The flexible I/O fabric in Diamond Rapids includes I/O PHYs, I/O cache, accelerators, snoop filters, and interconnect logic. These elements are designed to improve data movement between CPUs, accelerators, memory, and external devices. For modern AI data centers, this is just as important as raw CPU core count because AI infrastructure depends heavily on fast communication between compute engines.
Intel is also placing strong emphasis on power and thermal management. Diamond Rapids includes new core idle power states with L2 cache retention, priority core turbo support, memory thermal management based on MR4, and low-power states for both UXI and PCIe interfaces. There is also use-case-based power direction for I/O and memory, allowing the chip to better allocate power depending on workload demands.
Early platform information points to high-end Diamond Rapids systems reaching up to 650W TDP on an LGA 9324 platform. Multi-socket support is expected, making the chips suitable for dense enterprise servers and large-scale data center deployments. While 650W is a substantial power target, it reflects the direction of the server market, where CPUs are being asked to support more cores, more memory bandwidth, and much faster connectivity for AI-era workloads.
Diamond Rapids is expected to compete against AMD’s EPYC Venice platform and emerging CPU offerings connected to AI infrastructure from NVIDIA. Intel is also reportedly working on custom x86 server products with advanced accelerator connectivity as large AI companies diversify their CPU options across both x86 and Arm platforms.
The timing of Diamond Rapids is important. Enterprise AI is moving beyond simple inference and training support into more advanced agentic AI systems, where software agents can plan, reason, execute tasks, and interact with business systems. These workloads require a mix of high single-threaded performance, high core density, enormous memory bandwidth, and fast I/O. Intel is clearly designing Diamond Rapids with this shift in mind.
After Diamond Rapids, Intel plans to introduce Coral Rapids. That future Xeon generation is expected to bring back SMT support and may arrive around 2028, though rising demand for CPUs in agentic AI infrastructure could influence Intel’s schedule. Intel previously considered an 8-channel Diamond Rapids variant but reportedly shifted focus toward the larger 16-channel platform to better serve high-end server demand.
Overall, Intel Diamond Rapids looks like a major step forward for the Xeon roadmap. With up to 256 P-Cores, Intel 18A-P manufacturing, 16-channel memory, PCIe 6.0, CXL 3.0, advanced chiplet packaging, and a huge shared cache design, the platform is being built for the next wave of AI and cloud computing. If Intel delivers on its performance, efficiency, and scalability goals, Diamond Rapids could become one of the company’s most important data center CPU launches in years.
