AMD EPYC Verano and Venice-X CPUs Set to Push Zen 6 Deeper Into AI and HPC in 2027
AMD is preparing a major expansion of its EPYC server CPU family in 2027, with two new Zen 6-based platforms aimed directly at the fast-growing demands of artificial intelligence, high-performance computing, and large-scale cloud infrastructure. The company has confirmed EPYC Verano and EPYC Venice-X, two processor lines designed for different but equally demanding workloads.
The announcement shows how AMD plans to broaden its data center strategy beyond traditional server performance. As AI systems become more complex and HPC workloads require more memory bandwidth, cache, and efficiency, AMD is positioning Zen 6 as a flexible architecture that can serve both compute-heavy and memory-sensitive environments.
EPYC Venice-X targets high-performance computing with 3D V-Cache
One of the most important additions to AMD’s next-generation EPYC lineup is Venice-X. This chip family is built around Zen 6 and enhanced with AMD’s 3D V-Cache technology, giving it a major boost in addressable cache per core.
Venice-X is expected to play a major role in HPC environments where cache capacity can dramatically affect performance. Workloads such as scientific simulations, technical computing, financial modeling, data analytics, and engineering applications often benefit from larger caches because they reduce the need to constantly fetch data from system memory.
According to early platform details, Venice-X will be used in Microsoft Azure HXv2 instances in 2027. The processors are expected to feature 176 Zen 6 cores, high thread counts, clock speeds exceeding 5 GHz, and around 50% more addressable cache per core thanks to the stacked 3D V-Cache design.
The cache stacks are placed beneath the Zen 6 cores, allowing AMD to increase cache capacity without drastically changing the processor’s footprint. This approach has already proven valuable in previous EPYC “X” series processors, and Venice-X appears to continue that strategy for the next era of cloud-based HPC.
For customers running compute-dense workloads, Venice-X could become one of the most important Zen 6 server chips. The combination of high core counts, high clock speeds, and expanded cache makes it especially attractive for applications that need both raw throughput and low-latency data access.
EPYC Verano is designed for AI agents and memory-efficient infrastructure
While Venice-X focuses on HPC and cache-heavy workloads, EPYC Verano appears to be built for a different part of the AI market. AMD describes Verano as a processor designed for AI agents and future AI rack-scale systems.
The most notable feature of EPYC Verano is support for SOCAMM2 memory. This is a newer memory form factor that uses LPDDR5X DRAM modules to deliver high bandwidth, strong capacity, and improved power efficiency in a compact package.
That matters because AI infrastructure is increasingly limited not only by compute power but also by memory capacity, bandwidth, density, and energy use. Large AI models and agent-based systems require fast access to massive amounts of data, and SOCAMM2 gives system builders another way to increase memory density without dramatically increasing power consumption.
SOCAMM2 modules can reach very high capacities. Some current modules are already being produced with 256 GB densities, making them well-suited for large AI deployments. In rack-scale AI systems, where every watt and every square inch matters, compact high-capacity memory can be a major advantage.
AMD’s use of SOCAMM2 in EPYC Verano suggests that the company is preparing for a future where CPUs play a larger supporting role in AI systems. While GPUs and accelerators handle much of the heavy AI compute, CPUs still manage orchestration, data movement, inference pipelines, system memory, and agent-based workloads. Verano appears to be built with that future in mind.
Zen 6 will cover a wide range of data center workloads
AMD’s 2027 roadmap points to a broader Zen 6 EPYC lineup built for multiple market segments. EPYC Venice and Venice-Dense are expected to arrive earlier, while Verano and Venice-X will expand the family with more specialized designs.
The Venice family is expected to use TSMC’s 2nm process and support the SP7 platform, with high memory bandwidth through DDR5-8000+ and a large number of PCIe Gen 6 lanes. Venice-Dense is expected to push core counts much higher, reportedly up to 256 cores and 512 threads, making it suitable for cloud-native workloads, virtualization, and highly parallel server tasks.
Standard Venice is expected to focus on a balance of performance and efficiency, with up to 96 Zen 6 cores and support for high-speed memory and next-generation I/O. Venice-X then adds 3D V-Cache for HPC customers, while Verano introduces a different direction with SOCAMM2 LPDDR5X memory for AI rack systems.
This layered strategy allows AMD to target cloud providers, enterprise customers, AI infrastructure builders, and HPC operators with specialized EPYC products instead of relying on a single server CPU design.
LPDDR memory demand could tighten further
The move toward SOCAMM2 and LPDDR5X in AI infrastructure also raises an important industry concern: memory supply.
LPDDR memory is already widely used in smartphones, laptops, compact PCs, and other power-efficient devices. As AI servers and rack-scale systems begin adopting LPDDR-based memory modules in larger quantities, demand could rise sharply.
That could create additional pressure on the memory supply chain. If major AI platforms consume more LPDDR5X for server systems, the impact may extend beyond data centers. Smartphones, consumer electronics, notebooks, and other devices that rely on low-power DRAM could face tighter availability or higher costs if supply does not keep pace.
This is one reason SOCAMM2 is such an important development. It offers strong benefits for AI infrastructure, but widespread adoption could reshape how memory manufacturers allocate production between consumer devices and data center systems.
AMD’s EPYC roadmap shows rapid server evolution
AMD’s EPYC family has evolved quickly over the past several years. Naples launched the first EPYC generation in 2017 with Zen 1, followed by Rome with Zen 2, Milan and Milan-X with Zen 3, Genoa, Genoa-X, Bergamo, and Siena with Zen 4, and Turin with Zen 5.
The upcoming Zen 6 generation continues that pattern with Venice, Venice-Dense, Venice-X, and Verano. Each generation has increased core counts, cache capacity, memory bandwidth, and platform capabilities.
The expected jump to PCIe Gen 6, DDR5-8000+ memory support for Venice-class processors, and very high core counts shows how aggressively AMD is scaling EPYC for future workloads. Meanwhile, Verano’s SOCAMM2 support suggests AMD is willing to explore new memory architectures to address the needs of AI systems.
Why EPYC Verano and Venice-X matter
The arrival of EPYC Verano and Venice-X in 2027 could mark an important shift in AMD’s data center strategy. Instead of focusing only on general-purpose server CPUs, AMD is building more targeted processors for the workloads shaping the future of computing.
Venice-X is aimed at customers who need more cache, higher clocks, and strong Zen 6 compute performance for HPC and technical workloads. Verano, on the other hand, is designed for AI rack infrastructure, AI agents, and memory-efficient systems that require dense, high-bandwidth LPDDR-based memory.
Together, these processors show that the next generation of EPYC CPUs will not be defined by core counts alone. Cache design, memory form factor, power efficiency, platform scalability, and AI readiness are becoming just as important.
If AMD delivers on the performance and efficiency expectations surrounding Zen 6, EPYC Verano and Venice-X could become key products in the 2027 data center market, especially as cloud providers, AI companies, and HPC operators look for more specialized hardware to handle increasingly complex workloads.
