Google is getting ready to introduce a fresh wave of custom AI hardware with its next-generation Tensor Processing Unit lineup, known as TPUv8. According to multiple media and supply-chain reports, the TPUv8 family is expected to take the spotlight at Google Cloud Next, scheduled for April 22–24, 2026. The new chips are positioned to succeed Google’s current TPUv7 “Ironwood” accelerators, which have been in market since 2025.
What makes this launch especially notable is that TPUv8 is shaping up as a two-chip strategy built around distinct AI workloads. Instead of a single design trying to do everything, Google is reportedly splitting the lineup into dedicated options for AI training and AI inference—two tasks that demand very different performance, power, and cost profiles in modern data centers.
The first chip is TPUv8i, codenamed “Zebrafish.” This model is described as a cost-efficient inference accelerator, built to run trained AI models at scale. Inference is the “deployment” side of AI—handling real-time responses, search, recommendations, assistants, and large-scale automation—so efficiency and throughput per dollar matter hugely. Reports suggest TPUv8i will be designed by MediaTek.
The second chip is TPUv8t, codenamed “Sunfish,” and it’s aimed at high-performance AI training workloads. Training is the compute-heavy phase where large models are created and refined, and this is where organizations push for maximum performance, faster time-to-train, and improved scaling across data center infrastructure. TPUv8t is reportedly being designed by Broadcom.
Another interesting detail: despite earlier expectations that another major chip partner might be involved in Google’s next TPU generation, current information points instead to MediaTek and Broadcom leading the two TPUv8 variants. That shift hints that any additional partnerships could be targeting a different custom accelerator project or a future TPU platform beyond TPUv8.
Beyond the accelerators themselves, TPUv8 is expected to be closely tied to Google’s in-house server CPU strategy. Reports indicate both TPUv8 chips will be tightly integrated with Google’s Axion Arm CPUs. Axion is based on Arm’s Neoverse N3 platform (Armv9.2), and it has been deployed since 2024. If this integration is central to TPUv8 systems, it reinforces Google’s push toward vertically optimized AI servers—pairing custom CPUs with custom accelerators to improve performance, efficiency, and platform control across Google Cloud and internal AI infrastructure.
TPUv8’s reveal could also ripple well beyond Google’s own racks. Supply-chain expectations suggest the new TPU platform may drive increased demand across key data center and semiconductor-adjacent segments. That includes areas commonly upgraded when next-gen AI clusters roll out, such as high-speed optical networking, optical switching, power delivery systems, and liquid cooling—especially as AI training hardware continues to push thermal and power limits in dense server deployments.
At the same time, there’s a catch that often comes with large AI infrastructure expansions: supply pressure. With demand for AI accelerators already intense across the industry, major procurement for a global TPUv8 rollout could further tighten availability for surrounding components and manufacturing capacity. In other words, TPUv8 isn’t just a product refresh—it may also be a meaningful demand event for the broader ecosystem that supports hyperscale AI computing.
If the reported timeline holds, Google Cloud Next this week should clarify how TPUv8 is positioned, what performance and efficiency gains it brings over TPUv7, and how Google plans to scale training and inference across its worldwide AI and cloud infrastructure.
