Google and MediaTek Reportedly Team Up on TPUv9 “Triggerfish” for the Next Wave of Agentic AI
Google is reportedly preparing a major step forward in custom AI silicon with its next-generation TPUv9 chip, codenamed “Triggerfish.” The chip is said to be designed in collaboration with MediaTek and aimed at the fast-growing Agentic AI market, where AI systems need to reason, plan, act, and adapt across complex workloads.
The biggest change with Triggerfish is its focus on combining AI training and inference capabilities on a single chip. In previous generations, Google separated its Tensor Processing Unit lineup into chips optimized for different tasks. The TPUv8 family, for example, reportedly included the inference-focused v8i “Zebrafish,” developed with MediaTek, and the training-focused v8t “Sunfish,” developed with Broadcom.
With TPUv9, Google appears to be moving toward a more unified AI accelerator strategy. Instead of using separate chips for training models and running them at scale, Triggerfish is expected to handle both workloads in one package. This could make it especially valuable for AI agents, reinforcement learning, real-time decision-making systems, and large-scale cloud AI services.
According to industry reports, MediaTek is expected to play a key role again in Google’s TPU roadmap. The TPUv9 series is reportedly planned for mass production beginning in the third quarter of 2027, with “Humufish” expected to arrive first, followed by Triggerfish in the fourth quarter of 2027. Volume production for both chips is expected to ramp up in 2028.
A Unified AI Chip for Training and Inference
The TPUv9 Triggerfish is expected to introduce several important upgrades over Google’s current TPU designs. One of the most notable improvements is a much larger SRAM cache, reportedly two to three times bigger than before. More SRAM can help reduce data movement, improve latency, and increase efficiency when handling demanding AI workloads.
This matters because modern AI systems, especially agentic AI applications, require fast access to data during reasoning, planning, and execution. A larger on-chip memory pool can help the processor keep more information close to the compute units, improving performance and reducing dependence on external memory.
Triggerfish is also said to include a new CPU tile added by MediaTek. This CPU tile is expected to help manage workload switching between training and inference. By placing this CPU tile in the same package as the main compute die, Google could improve coordination between different parts of the chip and make the accelerator more flexible for mixed AI workloads.
This design approach suggests that Google is not simply building a faster TPU. It is building a more adaptive AI processor that can support the evolving needs of cloud AI, AI agents, and next-generation machine learning systems.
Why Agentic AI Needs a Different Kind of Hardware
Agentic AI is becoming one of the most important trends in artificial intelligence. Unlike traditional AI models that respond to single prompts, AI agents can perform multi-step tasks, interact with tools, make decisions, and refine their actions over time.
That creates new pressure on AI hardware. These systems often need a mix of inference, training-like adaptation, memory access, and rapid task switching. A chip that can efficiently support both training and inference could give Google an advantage in building infrastructure for more advanced AI services.
The TPUv9 Triggerfish appears to be designed with this shift in mind. By combining larger SRAM, advanced memory support, and a dedicated CPU tile, the chip could help Google maximize effective compute rather than only increasing raw performance numbers.
HBM4E Memory and Advanced Packaging
Triggerfish is expected to use HBM4E memory, which would place it among the most advanced AI accelerator designs planned for the coming years. High-bandwidth memory is essential for AI chips because large models require enormous amounts of data to move quickly between memory and compute units.
Meanwhile, another TPUv9 chip, Humufish, is reportedly expected to use HBM4 memory. Humufish is also said to use Intel’s EMIB packaging technology. EMIB, or Embedded Multi-die Interconnect Bridge, is designed to connect multiple chiplets efficiently inside a package. Compared with some other 2.5D packaging approaches, EMIB is often viewed as a more flexible and scalable option that can help reduce cost and improve production efficiency.
Reports suggest Humufish may use a main compute die designed by Google, while MediaTek may handle the I/O and back-end design. This highlights how Google’s TPU strategy is becoming increasingly dependent on deep partnerships across chip design, packaging, and manufacturing.
TSMC Manufacturing Still Expected, Intel Packaging Possible
There have been reports suggesting that some of Google’s future TPU chips could involve Intel manufacturing capacity, potentially covering millions of units. However, current industry analysis indicates that the chips are still expected to be manufactured by TSMC, while Intel may be involved mainly on the packaging side.
This kind of split would make sense in today’s semiconductor market. TSMC remains the leading manufacturer for advanced AI chips, but its capacity is under heavy demand from major customers across the industry. NVIDIA, AMD, Apple, and other large chipmakers are all competing for advanced process and packaging resources.
Because of these bottlenecks, Google may be looking for ways to diversify parts of its supply chain. Using Intel packaging for certain TPUv9 products could help reduce pressure on production and improve scalability as demand for AI infrastructure continues to rise.
Google’s Growing Custom AI Silicon Strategy
Google has been investing in custom AI chips for years, and TPUv9 appears to represent another major evolution in that strategy. Instead of relying entirely on general-purpose GPUs, Google has built its own Tensor Processing Units to optimize AI workloads across its cloud and internal services.
The TPUv8 generation showed a more specialized approach, with separate designs for training and inference. TPUv9, especially Triggerfish, appears to shift toward a broader and more integrated design. This could give Google more flexibility as AI workloads become less predictable and more dynamic.
If Triggerfish delivers on expectations, it could become an important part of Google’s AI infrastructure in 2028 and beyond. The ability to train, infer, switch workloads, and support AI agents on a single chip could help Google improve performance, efficiency, and total cost of ownership across large-scale AI deployments.
What Triggerfish Could Mean for the AI Chip Market
The AI hardware race is intensifying, and Google’s TPUv9 Triggerfish could become a serious competitor in the next generation of AI accelerators. While GPUs continue to dominate much of the market, custom silicon is becoming increasingly important for companies that operate massive AI platforms.
Google’s advantage is that it designs chips for its own software, data centers, and AI services. That gives the company more control over the full stack, from models and infrastructure to silicon and deployment.
With MediaTek reportedly contributing to the design, TSMC expected to handle manufacturing, and Intel potentially supporting advanced packaging, TPUv9 could also reflect a more distributed and resilient supply-chain model.
The Bottom Line
Google’s TPUv9 Triggerfish is shaping up to be a major next-generation AI chip built for the age of Agentic AI. By combining training and inference on a single processor, adding a larger SRAM cache, using advanced HBM4E memory, and introducing a CPU tile for workload management, Triggerfish could offer a more flexible and powerful solution for modern AI systems.
Mass production is reportedly expected to begin in late 2027, with broader volume ramping in 2028. If the timeline holds, Google’s TPUv9 family could play a key role in powering future AI agents, cloud AI services, and large-scale machine learning workloads.
