CXMT Targets 4F² DRAM Breakthrough by 2026, Putting Pressure on Samsung, SK hynix, and Micron
China’s ChangXin Memory Technologies, better known as CXMT, appears to be accelerating its push into advanced DRAM at a pace that could shake up the global memory market. The company is reportedly preparing to introduce a server-focused DDR5 RDIMM product based on next-generation 4F² memory cell architecture before the end of 2026.
If achieved, that timeline would place CXMT roughly two years ahead of Samsung’s expected rollout of similar DRAM architecture, giving the Chinese memory maker a potentially significant lead in one of the industry’s most important technology transitions.
CXMT’s latest ambitions were outlined by company president Dr. Cao Kanyu during a speech at the 4th Integrated Chip and Chiplet Conference in Shanghai. He discussed the company’s progress on 4F² DRAM, as well as advanced packaging and manufacturing technologies such as hybrid bonding.
The announcement is notable because the DRAM industry has long been dominated by Samsung, SK hynix, and Micron. CXMT has traditionally been seen as a fast-rising challenger, but a successful move to 4F² architecture in server memory would signal a major step forward in both design capability and manufacturing maturity.
The product in question is expected to be a DDR5 RDIMM aimed at servers and data centers. RDIMM, short for Registered Dual In-Line Memory Module, is widely used in enterprise systems because it includes a register, or buffer, that temporarily holds signals from the CPU before passing them to memory chips. This reduces electrical load on the memory controller and allows servers to support more memory modules with higher capacities.
That makes RDIMM technology critical for cloud computing, artificial intelligence workloads, enterprise databases, and high-performance computing. As demand for server memory continues to rise, a denser and more efficient DRAM design could give CXMT an important foothold in a lucrative segment of the market.
The key innovation is the 4F² DRAM cell architecture. In conventional DRAM designs, the transistor and capacitor that make up each memory cell are arranged largely across the chip surface. With 4F², the cell components are stacked more vertically, allowing each memory cell to occupy a much smaller footprint.
The term 4F² refers to a cell area that measures four times the square of the minimum feature size. In simpler terms, it allows memory makers to pack more cells into the same silicon area. Moving from a 6F² design to a 4F² layout can reduce the memory cell area by around one-third at the same feature size.
This matters because DRAM scaling has become increasingly difficult. As process nodes shrink, manufacturers face greater challenges with leakage, power consumption, signal integrity, and cost. A denser cell architecture can help extend DRAM scaling without relying solely on aggressive lithography improvements.
Industry estimates suggest that 4F² architecture could increase DRAM cell density by roughly 30% to 50%, depending on implementation. For data centers and AI infrastructure, that could translate into higher-capacity memory modules, improved power efficiency, and better performance per watt.
CXMT has not arrived at this point overnight. The company has been researching 4F² DRAM for several years and published early work on the architecture in 2021. Its upcoming implementation is expected to be tied to its newer 15nm-class G5 DRAM process, though the first version may not be a fully mature implementation of the technology. Instead, it could be a transitional or partial version designed to bring some of the benefits of 4F² while reducing manufacturing risk.
The company has also been advancing its manufacturing techniques. CXMT is believed to have moved into mass production of its G5 generation, which is significant because it reportedly involves SAQP, or self-aligned quadruple patterning. This technique allows chipmakers to create finer circuit patterns without relying entirely on the most advanced lithography tools.
After G5, a transition to G6 is expected to be a natural next step before the industry moves more broadly toward monolithic 3D DRAM designs. These future architectures could reshape memory manufacturing by stacking memory structures in new ways, similar in concept to how 3D NAND transformed the storage market.
Another important part of CXMT’s roadmap is High-k Metal Gate technology, often shortened to HKMG. This manufacturing approach replaces older silicon-based insulating materials with high-k materials such as hafnium oxide. The result is better control of current leakage, lower wasted heat, improved power efficiency, and faster transistor switching.
HKMG is already important in advanced logic chips, and its use in DRAM becomes increasingly valuable as memory cells shrink. CXMT is reportedly applying HKMG to its G4 DRAM process, widely believed to be in the 1z-class generation, as well as to LPDDR5X memory products. LPDDR5X is widely used in mobile devices, laptops, and other power-sensitive platforms, making efficiency gains especially important.
Beyond technology development, CXMT is also expanding aggressively on the production side. The company is expected to reach around 300,000 wafers per month in DRAM capacity by the end of this year through three 300mm fabrication plants, each capable of producing roughly 100,000 wafers per month.
CXMT is also targeting high-bandwidth memory, or HBM, a key component for AI accelerators and advanced GPUs. Its HBM-focused production capacity could reach around 50,000 wafers per month by the end of 2026. That would place the company in a strategic position as demand for AI memory continues to grow rapidly.
The expansion does not stop there. CXMT is building additional fabrication facilities in Shanghai and Hefei, which could eventually lift total production capacity to about 600,000 wafers per month. If these plans stay on track, CXMT could become one of the world’s largest DRAM producers by the end of the decade and may even surpass Micron in volume output around 2030.
Samsung, meanwhile, is expected to introduce 4F² DRAM with its B1b process, also known as D0a. This is expected to be Samsung’s first sub-10nm DRAM manufacturing process. The company’s approach may involve separating the memory cell array and the peripheral driver circuitry onto different wafers, then joining them through wafer-to-wafer hybrid bonding.
Hybrid bonding allows extremely dense connections between stacked wafers and can improve performance and layout efficiency. However, it is also costly and complex. If Samsung relies heavily on this method for its next-generation DRAM, the resulting products could carry a significant price premium, especially in the early stages of production.
That creates an interesting competitive dynamic. If CXMT can bring a 4F²-based DDR5 RDIMM to market earlier and at competitive yields, it could pressure established DRAM leaders not only on technology timelines but also on pricing. However, execution will be critical. Advanced DRAM is difficult to manufacture at scale, and early announcements do not always translate into immediate commercial success.
Still, CXMT’s progress shows how quickly the memory landscape is changing. The company is no longer simply expanding capacity; it is attempting to compete at the architectural level, where the next major gains in density, power efficiency, and performance will be won.
For the global DRAM market, the implications are significant. A successful CXMT 4F² server memory product could increase competition in DDR5 RDIMM, accelerate the adoption of denser DRAM architectures, and push established players to move faster on their own roadmaps.
With AI servers, cloud infrastructure, and enterprise computing driving unprecedented demand for memory, the race to develop next-generation DRAM is becoming more important than ever. CXMT’s 2026 target suggests that China’s leading memory manufacturer wants to be viewed not just as a volume player, but as a serious contender in advanced memory technology.
