Micron Challenges 4F² DRAM Hype as CXMT and YMTC Push Ahead With New Memory Architecture
The race to build denser, faster, and more power-efficient DRAM is entering a critical phase, and one of the industry’s most talked-about technologies is now facing sharp criticism from Micron. While Chinese memory makers CXMT and YMTC appear to be betting heavily on 4F² memory cell architecture to overcome manufacturing limits tied to DUV lithography, Micron is taking a very different view.
At the center of the debate is 4F² DRAM, a next-generation memory cell design that promises major gains in density by changing how memory cells are arranged. Instead of placing the transistor and capacitor of a DRAM cell side by side in a traditional horizontal layout, 4F² stacks key components vertically. This allows each memory cell to occupy a smaller surface area, theoretically improving chip density without requiring the most advanced lithography tools.
In simple terms, the “4F²” name refers to a cell area equal to four times the square of the minimum feature size. The structure is based on two bitlines and two wordlines, the electrical pathways used to control and access memory cells. By shrinking the cell footprint, DRAM manufacturers could potentially reduce memory cell area by around 30% to 40% while increasing integrated circuit density by roughly 30% to 50%.
That sounds like a major breakthrough for the DRAM industry, especially for companies that do not have easy access to extreme ultraviolet, or EUV, lithography. But Micron is warning that the real-world path may not be as promising as it appears on paper.
During a recent technology webinar, Micron said it has studied 4F² for more than two decades and does not see a viable scaling roadmap. Scott DeBoer, Micron’s president and chief technology and product officer, argued that the architecture faces “fundamental problems” as manufacturers try to scale it further. He also suggested that the density advantage of 4F² over the more established 6F² DRAM cell design has been overstated.
Micron’s position is important because it suggests the company is not convinced 4F² is the future of DRAM scaling. Instead, Micron appears to be looking toward 3D DRAM as a more practical long-term direction. 3D DRAM, like 3D NAND before it, aims to achieve greater density by moving beyond two-dimensional scaling and building memory structures vertically in more advanced ways.
However, not every memory manufacturer shares Micron’s skepticism.
CXMT, one of China’s leading DRAM producers, is reportedly preparing to introduce a DDR5 RDIMM product based on 4F² memory cell technology before the end of 2026. If CXMT can overcome the technical challenges tied to 4F² manufacturing, the company could effectively move from a 1c-class DRAM process to a 1d-class node. That would be a meaningful step forward in process shrinkage and could help narrow the gap with more established global memory players.
YMTC is also said to be exploring the use of 4F² technology in DRAM, expanding beyond its better-known work in NAND flash. Industry research indicates that YMTC has been developing a second-generation 16 Gb LPDDR5 DRAM product with a speed of 7500 MT/s. This work has reportedly been taking place at Fab 2 with a monthly capacity of around 5,000 wafers.
More notably, YMTC is also said to be working on a faster 9600 MT/s version using a vertical channel transistor, or VCT, 4F² cell structure. Mass production for this design is reportedly planned for Fab 3. If successful, this would mark a significant step for YMTC as it attempts to apply advanced stacking and interconnect concepts beyond NAND and into the DRAM market.
The push from CXMT and YMTC reflects a larger challenge facing Chinese semiconductor manufacturers. With limited access to the most advanced EUV lithography systems, companies relying on DUV tools must find alternative ways to keep scaling memory chips. 4F² is one of those alternatives because it promises density improvements through architectural changes rather than pure lithography advancement.
Another technology being explored is High-k Metal Gate, commonly known as HKMG. This approach replaces older silicon-based insulating materials with high-k materials such as hafnium oxide. The benefit is reduced current leakage, lower wasted heat, better power efficiency, and faster transistor switching. For DRAM products such as DDR5 and LPDDR5, these advantages can translate into higher speeds and improved energy efficiency.
HKMG could play an important role in helping memory manufacturers push performance higher while controlling power consumption. However, integrating HKMG with advanced DRAM cell structures is complex, and successful mass production remains a major technical hurdle.
The current split in industry strategy is clear. Micron is signaling that 4F² may not offer a reliable long-term scaling path and is instead focusing on future technologies such as 3D DRAM. Meanwhile, CXMT and YMTC appear willing to take the risk, treating 4F² as a practical route to improve density and performance despite lithography limitations.
The outcome could have major consequences for the global DRAM market. If Micron is right, 4F² may prove to be a difficult detour rather than a breakthrough. But if CXMT or YMTC manages to solve the scaling and production challenges, the technology could give them a powerful tool to compete in DDR5, LPDDR5, and future high-performance memory segments.
For now, 4F² DRAM remains one of the most closely watched battlegrounds in semiconductor manufacturing. It represents both a technical gamble and a strategic opportunity. Whether it becomes a genuine leap forward or a costly dead end will depend on how well memory makers can turn theory into reliable, high-volume production.
