TSMC Moves Toward Glass Substrates for Next-Generation AI Chip Packaging
TSMC is reportedly taking early steps to build a supply chain for glass substrates, a key material that could play an important role in future advanced chip packaging. The move is tied to the company’s longer-term development of chip-on-panel-on-substrate, or CoPoS, packaging technology, while also supporting more advanced versions of its current chip-on-wafer-on-substrate, known as CoWoS.
According to supply chain sources, TSMC is working with partners including Innolux and Ibiden as it explores how glass substrates can improve packaging for high-performance computing chips. These efforts are focused on solving several major challenges facing next-generation processors, especially those used in artificial intelligence, data centers, and advanced GPU platforms.
The main issues being studied include heat management, signal transmission, electrical performance, and package warpage. Warpage refers to the bending or twisting of chip packaging materials, which can affect manufacturing yield, reliability, and overall chip performance. As AI chips become larger and more complex, controlling these physical and electrical characteristics becomes increasingly important.
Glass substrates are attracting attention because they may offer better stability than traditional organic substrates. Reports suggest that using glass can reduce package warpage by around 16%. Other performance-related measurements also showed improvement, including thermal expansion, resistance, and inductance, which reportedly dropped by 19%, 27%, and 42%, respectively.
These improvements matter because advanced AI processors generate enormous amounts of heat and require extremely fast signal movement between different components. Better thermal behavior and improved electrical characteristics could help future chip packages support higher performance without sacrificing reliability.
For now, however, glass substrates are not expected to enter mass production immediately. The technology is still in the development and testing stage, and manufacturers must overcome several technical hurdles before it can be widely adopted.
One of the biggest challenges is conductivity. Glass itself does not conduct electricity, so chipmakers need to create vertical conductive pathways, known as vias, through the glass. These pathways allow electrical signals and power to move through the substrate. Producing these vias at high precision and scale is a difficult manufacturing task, especially for advanced semiconductor packaging.
TSMC’s reported test sample used a substrate with a glass core. The sample did not show warpage or peeling problems that would negatively affect yield, which is an encouraging sign for the future of the technology. If development continues successfully, glass substrates could become suitable for high-end AI GPUs and other demanding high-performance computing products.
The interest in glass substrates comes as demand for advanced packaging continues to surge. AI accelerators and next-generation GPUs require large packages that can combine multiple chips, high-bandwidth memory, and other components into a single system. This has made packaging technology just as important as transistor scaling in the race for better computing performance.
Even with its work on glass and panel-level packaging, TSMC is expected to continue relying heavily on CoWoS for advanced AI chips in the near term. Company executives have previously indicated that CoWoS remains the preferred solution because of its maturity and ability to handle the geometric complexity of today’s most advanced semiconductor designs.
CoPoS and glass substrate technology may become more important over time as chip packages grow larger and more complex. Panel-level approaches could eventually help improve production efficiency and support larger package sizes, but they must first meet strict performance, reliability, and yield requirements.
TSMC’s early supply chain activity suggests that the company is preparing for a future where advanced packaging materials become a major competitive advantage. As AI workloads continue to expand, chipmakers will need packaging solutions that can deliver better heat dissipation, stronger signal integrity, and improved structural stability.
Glass substrates may not replace existing materials overnight, but they could become a critical part of the next generation of AI chip packaging. For TSMC, building the supply chain now could help position the company ahead of rising demand for more powerful and efficient high-performance computing processors.
