Samsung’s 2nm Gate-All-Around process is shaping up to be a major leap in performance and efficiency, but the company says the era of easy wins from simple node shrinking is over. Instead, it’s betting on a broader strategy that optimizes chip design and manufacturing together to unlock bigger gains at advanced nodes.
At an industry workshop in Seoul, Samsung’s foundry leadership explained that while moving from one node to the next still delivers around a 10–15% improvement in speed and area, those incremental gains aren’t enough on their own. In fact, even a 1–2% edge can decide which process customers choose, making every percentage point matter at the cutting edge.
That’s why the focus is shifting to DTCO, short for Design and Process Integration Optimization. This approach brings design and process engineering under one umbrella to remove layout constraints, pack cells more efficiently, and reduce power and area. According to industry figures cited at the event, DTCO contributed roughly 10% of overall performance uplift at 7nm, and its share is expected to rise to about 50% at 3nm and below. Both Samsung and its biggest rival are investing heavily in dedicated DTCO teams to pursue these gains in parallel with standard process scaling.
A key part of Samsung’s progress has been the move from FinFET to Gate-All-Around (GAA) transistors. GAA gives the company tighter current control, which translates to better performance and power efficiency at small geometries. While the first 3nm GAA generation faced yield challenges, Samsung says its 2nm node is showing strong promise and a wider set of improvements.
DTCO in practice means working closely with customers and designers to reimagine the flow. Engineers examine process constraints and explore alternatives driven by design requests from major clients, including automakers and AI-focused companies. The result is smarter placement, leaner surface area, and architectures tuned to real-world workloads rather than theoretical best cases.
Samsung is also deploying artificial intelligence to automatically propose new cell structures with smaller footprints and lower power draw. The company expects DTCO to expand further into SPCO (System-Process Co-Optimization) and SDTCO (System-Design-Process Co-Optimization), weaving system-level requirements into the optimization loop to wring out even more performance per watt.
On the roadmap side, Samsung has completed the basic design of its second-generation 2nm GAA process, with a third iteration, SF2P+, targeted within about two years. There are indications the foundry may be prioritizing deeper DTCO-driven refinements to its 2nm family, which could explain a slower push toward a 1.4nm node. Rather than racing to the next label, the strategy appears to be maximizing practical performance, power, and area advantages that matter to customers deploying chips at scale.
Bottom line: as raw scaling hits diminishing returns, the winners at 2nm and beyond will be the companies that co-optimize everything—transistor architecture, design rules, cell libraries, and even system requirements. Samsung’s bet on DTCO, GAA, and AI-assisted cell design signals exactly that direction.
