Pat Gelsinger Criticizes HBM Again as AI Demand Pushes DRAM Shortages Toward 2028
Former Intel CEO Pat Gelsinger has once again taken aim at high-bandwidth memory, arguing that while HBM has become essential for modern AI accelerators, it remains a deeply imperfect solution. His latest comments come as the memory industry faces mounting pressure from artificial intelligence demand, with manufacturers warning that DRAM supply constraints could last into early 2028.
In a recent interview, Gelsinger described HBM as a “hideous” and “terrible” form of memory, while also admitting that it is currently the best option available for the workloads driving the AI boom. His criticism centers on several technical limitations, including low bit density, thermal challenges, power consumption, and physical bandwidth constraints.
HBM, short for high-bandwidth memory, is widely used in advanced GPUs and AI accelerators because it can deliver massive data transfer rates. This makes it highly valuable for artificial intelligence workloads, where processors constantly move huge amounts of data between compute engines and memory. However, Gelsinger argues that the design comes with serious trade-offs.
One of the biggest issues is what he referred to as the “shoreline bandwidth” problem. In simple terms, this bottleneck is caused by the limited physical space around the edge of a processor die. HBM relies on extremely wide memory interfaces, meaning it needs a large number of physical connections between the processor and the memory stacks.
The physical layer interface, often called the PHY, acts as the bridge between the logic chip and the HBM stack. Because HBM uses a wide and relatively slower design, it requires many parallel connections. HBM3 and HBM3E use a 1,024-bit bus, while HBM4 increases that to 2,048 bits. Each of these interfaces requires a large number of micro-bumps, drivers, receivers, and routing structures.
That creates a major layout challenge. The PHY takes up a significant block of silicon along the edge of the compute die. Since only a limited amount of edge space is available, there is a hard limit on how many HBM stacks can be placed next to a chip. In many advanced chip designs, only two edges of the die are typically available for HBM, while the remaining sides are needed for other system input and output connections.
Thermals add another complication. HBM is placed very close to powerful processors, and DRAM does not perform well under excessive heat. As power consumption rises, the HBM interface itself can become a major heat source. Research has shown that once HBM power usage climbs beyond a certain level, heat generated by the PHY can become a leading cause of memory thermal stress, reducing overall efficiency.
Gelsinger also criticized HBM’s bit density. HBM stacks are built by connecting multiple DRAM dies vertically using through-silicon vias, or TSVs. These vertical connections enable high bandwidth, but they also take up space inside the memory die. As a result, each individual DRAM die can store fewer bits than a more conventional memory design. While the full stack can offer impressive density per square millimeter, the underlying architecture involves compromises.
This is not the first time Gelsinger has spoken negatively about HBM. Earlier this year, he called it a “lousy” memory technology, acknowledging that such remarks might not please memory manufacturers but insisting that the architecture has clear drawbacks.
Despite the criticism, HBM remains central to the AI hardware race. Leading AI chips rely on it because conventional DRAM cannot provide the same bandwidth needed for large language models, machine learning training, and high-performance inference. For now, the industry has few alternatives that can match HBM’s combination of speed and proximity to compute engines.
The growing shift toward HBM production is also reshaping the broader memory market. HBM requires significantly more wafer capacity than comparable commodity DRAM products. Industry estimates suggest that producing HBM can consume roughly three times as many wafers as standard DRAM of a similar capacity.
That production burden is one reason conventional DRAM supply has tightened. As memory makers allocate more capacity to high-margin HBM for AI accelerators, fewer resources are available for mainstream DRAM used in PCs, servers, smartphones, and other devices.
Memory manufacturer Nanya has warned that AI demand is creating structural changes across the memory industry. According to the company, DRAM shortages are likely to continue until early 2028, suggesting that the current supply imbalance may not be a short-term cycle but a longer-lasting shift driven by AI infrastructure spending.
The situation highlights a major tension in the semiconductor market. HBM is increasingly necessary for AI performance, but it is expensive, difficult to manufacture, thermally challenging, and capacity-intensive. At the same time, the industry’s pivot toward HBM is putting pressure on traditional DRAM availability, potentially affecting pricing and supply across consumer and enterprise technology markets.
For AI chipmakers, HBM remains the best available memory option despite its flaws. For the rest of the industry, the race to feed AI accelerators with faster memory could mean continued DRAM shortages, higher costs, and a more constrained supply chain for years to come.
