Fresh details about Intel’s upcoming Nova Lake processors are starting to paint a clearer picture of what the next-generation desktop and laptop lineup will look like, and the newest leak focuses on something enthusiasts love to dissect: compute tile die sizes.
According to the latest information shared online, Intel is preparing at least two major compute tile variants for Nova Lake based on an 8 P-core + 16 E-core configuration. What’s especially interesting is that the standard compute tile is actually a bit smaller than the comparable compute tile used in Arrow Lake, even as Intel continues expanding options for high-end models through larger cache designs and even dual compute tile layouts.
Nova Lake core configuration: what’s inside the compute tile
Nova Lake is expected to use 8 performance cores (P-cores) built on the Coyote Cove architecture and 16 efficiency cores (E-cores) based on Arctic Wolf. On top of that, the design also includes 4 LP-E (low-power efficiency) cores located on a low-power island. These LP-E cores aren’t meant for overclocking, but they can handle lightweight tasks efficiently and may even run alongside the E-core clusters, depending on how Intel configures specific models.
Another detail that stands out is how Intel is organizing the P-cores: the design groups them into clusters of two P-cores per cluster, with 4MB of L2 cache per cluster.
TSMC N2 process for Nova Lake compute tiles
One of the biggest platform notes is that Nova Lake compute tiles are reportedly being built on TSMC’s N2 process. That means these compute tiles won’t be using Intel’s 18A process in the way some people expected after hearing about future Intel roadmaps. There’s still mention of a possibility that an 18A compute tile could appear in some form later, but the current information points to two N2 compute tile designs.
Reported Nova Lake compute tile die sizes (standard vs big cache)
For the standard 8+16 compute tile (plus the 4 LP-E cores), the die size is said to be around 110mm². That’s slightly smaller than Arrow Lake’s compute tile, which is reported at 117.2mm².
But Intel is also expected to offer a big-cache version often described as a bLLC variant. This version adds a massive 144MB of cache per compute tile, and the size increase is significant: around 150mm². That makes the bLLC tile roughly 36.6% larger than the standard Nova Lake compute tile, and about 28% larger than Arrow Lake’s compute tile.
Dual compute tile Nova Lake chips could get very large
The leak also provides early figures for dual compute tile configurations, which would be used for higher-end SKUs. In terms of total compute tile area on the package:
A dual compute tile setup using standard (non-bLLC) tiles is estimated at about 220mm².
A dual compute tile setup using bLLC tiles could reach close to 300mm², with specs described as up to 52 cores and as much as 288MB of L3 cache (with a combined L2 + L3 cache figure stated in the 320MB range).
That’s a substantial amount of silicon dedicated just to compute tiles, but there’s a practical upside: the information suggests these configurations should still fit within the same package footprint and run on the same socket, meaning buyers likely won’t need a different platform just to use bLLC or dual-tile models.
How Nova Lake tile sizes compare to AMD Zen 5 and Zen 6 CCDs
The leak also puts Intel’s compute tile sizes into context by comparing them to AMD’s CCD approach.
AMD Zen 5 currently uses 8 cores per CCD with a die size around 71mm².
AMD Zen 6 is expected to move to as many as 12 cores per CCD at an estimated 76mm².
Compared with those figures, Intel’s standard 24-core Nova Lake compute tile (8P+16E) at roughly 110mm² is about 55% larger than a Zen 5 CCD, while packing roughly triple the core count. Against an estimated Zen 6 CCD, Nova Lake’s standard tile is about 44% larger while offering about double the cores.
The cache strategy is also different. AMD’s approach to adding extra cache relies heavily on stacked cache technology, allowing additional cache capacity without expanding the CCD footprint as dramatically. Intel, based on the current details, appears to be increasing tile area for its large-cache option rather than stacking cache for Nova Lake.
Quick summary of the reported die sizes
Intel Nova Lake 8P+16E standard compute tile: ~110mm²
Intel Nova Lake 8P+16E with +144MB cache (bLLC): ~150mm²
Intel Nova Lake dual compute tile (16P+32E total): ~220mm²
Intel Nova Lake dual compute tile with +288MB cache (bLLC): ~300mm²
AMD Zen 5 8-core CCD: ~71mm²
AMD Zen 6 12-core CCD (estimated): ~76mm²
Nova Lake-S vs Arrow Lake-S platform highlights (early picture)
Beyond tile sizes, the broader rumored specs suggest Nova Lake-S could scale dramatically higher than Arrow Lake-S. Nova Lake-S is associated with up to 52 cores and 52 threads, increased PCIe lane counts, faster DDR5 support, and a new socket (LGA 1954) compared to Arrow Lake’s LGA 1851. Power targets also look more aggressive at the high end, especially for dual compute tile parts, which are rumored to push far beyond typical mainstream desktop power levels.
Launch timing and why this matters
Nova Lake-S desktop CPUs and new 900-series motherboards are currently expected in the second half of 2026. If these figures hold, the next Intel vs AMD matchup could be one of the most interesting in years, with Intel leaning into tile-based scaling and big-cache variants while AMD counters with newer Zen 6 designs and its own platform updates.
For now, this die-size leak gives a useful glimpse into Intel’s priorities: better density on the standard tile, a clearly defined path for cache-heavy models, and a way to scale performance upward with dual compute tiles without forcing a separate socket or platform.
