Fresh rumors about Intel’s next desktop lineup suggest Nova Lake-S, expected to land under the “Core Ultra 400” branding, will lean heavily into a new cache-focused design for enthusiasts. The big headline is bLLC, short for “Big Last-Level Cache,” which is said to appear on at least four unlocked (overclocking-friendly) Nova Lake-S models. If accurate, this would mark a major push by Intel to boost gaming performance and responsiveness, especially in scenarios where extra cache can make a noticeable difference.
According to the latest claims, Intel is preparing two types of Nova Lake-S bLLC CPUs: higher-end dual compute tile chips and more mainstream single compute tile chips. In both cases, the emphasis is on dramatically expanding dedicated last-level cache capacity, potentially positioning these processors as direct rivals to AMD’s cache-stacked Ryzen “3D V-Cache” style chips that have earned a strong reputation in gaming.
The rumored unlocked Nova Lake-S bLLC lineup includes four configurations:
One dual compute tile model built from 2x 8+16 core tile layouts, said to reach 48 cores plus 4 LP-E (low-power efficiency) cores, for a total of 52 cores. This part is rumored to carry 288 MB of bLLC overall, split as 144 MB per compute tile.
A second dual compute tile model using 2x 8+12 tile layouts, said to reach 40 cores plus 4 LP-E cores, totaling 44 cores, also referenced with a 288 MB bLLC setup—though it’s unclear whether cache capacity stays the same on this variant or scales down.
A single compute tile model with an 8+16 layout, said to offer 24 cores plus 4 LP-E cores (28 total cores), paired with 144 MB of bLLC.
Another single compute tile model with an 8+12 layout, said to offer 20 cores plus 4 LP-E cores (24 total cores), also paired with 144 MB of bLLC.
One important detail: the bLLC figures are described as being in addition to the more typical per-tile cache levels (like L2 and L3). In other words, total cache on these chips could end up being extremely large, particularly on the dual tile models. That’s a clear signal Intel may be aiming to counter the advantages AMD has achieved with extra cache in gaming and latency-sensitive workloads.
The rumor also suggests Intel could roll out single compute tile versions first, then expand into dual compute tile territory later. That would make sense from a platform readiness and product rollout standpoint, especially if the more complex designs require tighter validation.
There’s also talk of platform implications. The same leak points to added challenges for motherboard makers due to the demands of bLLC-enabled processors, with next-generation boards potentially needing more advanced power delivery designs. These chips are expected to use a new LGA 1954 socket, meaning a new motherboard platform would be required.
Stepping back, the broader picture paints Nova Lake-S as a major leap over Arrow Lake-S on paper. Rumored specs for Nova Lake-S include up to 52 total cores (including LP-E cores), a much higher ceiling for PCIe lanes, faster DDR5 support targets, a higher maximum TDP rating, and a planned arrival sometime in 2026. By comparison, Arrow Lake-S is associated with lower maximum core counts and no bLLC support.
As always with pre-launch CPU leaks, nothing is final. Even the source behind the claim reportedly isn’t completely certain these plans won’t change. Still, the direction is hard to ignore: Intel appears to be working aggressively on a cache-forward desktop strategy to improve gaming performance and efficiency, directly addressing the area where AMD’s Ryzen cache-focused models have stood out in recent years.
