Cadence Certifies AI-Driven Design Flows for Intel 18A-P and Intel 14A Process Technologies
Cadence has announced that its AI-powered digital and custom reference flows, tools, and design solutions are now certified for Intel 18A-P and Intel 14A technologies. The certification is based on the latest Intel Foundry process design kits and gives chip designers a signoff-ready route for building advanced system-on-chips for artificial intelligence, high-performance computing, mobile, data center, and next-generation edge applications.
The move strengthens the ongoing collaboration between Cadence and Intel Foundry, particularly around advanced semiconductor design enablement. With chips becoming more complex and demand rising for greater performance-per-watt, certified design flows are becoming increasingly important for companies trying to move from concept to production silicon faster and with lower risk.
Cadence and Intel Foundry have been working together to optimize tools, design methodologies, and IP for Intel’s advanced manufacturing nodes. This includes support for key Intel process innovations such as RibbonFET gate-all-around transistor technology and backside power delivery features, including PowerVia and PowerDirect. These technologies are designed to improve power efficiency, performance, and routing flexibility for future chips.
For customers, the certification means Cadence’s design ecosystem is ready to support development on Intel 18A-P and Intel 14A with validated flows for implementation, verification, and final signoff. These workflows cover essential chip design stages such as synthesis, place-and-route, timing signoff, power signoff, physical verification, reliability verification, and analog/custom design.
By aligning Cadence’s AI-driven electronic design automation portfolio with Intel Foundry’s advanced process technologies, the companies aim to help design teams achieve stronger power, performance, and area results while shortening development cycles. This is especially important for AI accelerators, cloud computing chips, advanced mobile processors, and complex multi-die designs where efficiency and reliability are critical.
Intel Foundry’s leadership emphasized that ecosystem collaboration is essential as customers look to build differentiated products for the AI era. Certified design flows and silicon-validated IP can give chip developers more confidence when targeting next-generation process nodes, particularly when pursuing aggressive power, performance, and efficiency goals.
The new certification also reinforces Cadence’s role in the Intel Foundry Accelerator Ecosystem Alliance. As part of this program, Cadence is helping provide design enablement for advanced Intel Foundry nodes as well as scalable solutions for chiplet-based architectures. This is increasingly important as the semiconductor industry shifts toward multi-die packaging and heterogeneous integration to overcome traditional scaling limits.
Cadence and Intel Foundry have also collaborated on an advanced packaging reference design flow supporting Intel’s Embedded Multi-die Interconnect Bridge technologies, including EMIB and EMIB-T. This workflow is intended to simplify the integration of complex multi-chiplet systems by reducing unnecessary data conversion steps and enabling more parallel design activity.
The packaging flow also supports early analysis of thermal behavior, signal integrity, and power integrity across dies and packages. These capabilities are important for AI and HPC processors, where multiple chiplets must operate together efficiently under demanding power and performance conditions.
In addition to design flow certification, Cadence and Intel Foundry have validated IP test chips in silicon on Intel 18A using Cadence interface and memory IP. This demonstrates interoperability between Cadence IP, its AI-driven design flows, and Intel Foundry’s process technologies optimized for modern power delivery.
Intel 14A is expected to represent a major step forward beyond Intel 18A. Featuring RibbonFET 2 and PowerDirect, Intel 14A is designed to deliver higher performance at the same power level compared with Intel 18A. This could make it an attractive platform for future AI accelerators, cloud and edge HPC chips, premium mobile processors, and eventually applications in aerospace and government sectors.
Cadence described the partnership as a way to help customers turn ambitious chip architectures into reliable silicon more quickly. By combining certified EDA flows, silicon-validated IP, advanced packaging workflows, and Intel’s latest process technologies, the companies are positioning Intel 18A-P and Intel 14A as key platforms for future AI, HPC, and mobile innovation.
Cadence plans to showcase its certified Intel 18A-P and Intel 14A flows, design technology co-optimization methodologies, and advanced packaging solutions at the Design Automation Conference. Demonstrations are expected to highlight use cases across artificial intelligence, high-performance computing, and mobile markets.
For chip designers, the key takeaway is clear: Cadence’s certification for Intel 18A-P and Intel 14A provides a more mature and validated path for developing advanced semiconductors on Intel Foundry’s next-generation nodes. As demand grows for faster, more efficient, and more scalable silicon, certified AI-driven design flows could play a central role in bringing future processors and accelerators to market.
