Intel is positioning itself to take advantage of today’s surging DRAM demand by teaming up with a SoftBank subsidiary to develop a new memory standard known as Z-Angle Memory, or ZAM. With AI infrastructure spending accelerating and hyperscalers expanding data center capacity, memory has become one of the biggest pressure points in the supply chain. Limited global output and ongoing bottlenecks are fueling interest in alternative approaches, and Intel appears ready to re-enter the conversation in a serious way.
The effort to build ZAM is reportedly tied to work that began under the U.S. Department of Energy’s Advanced Memory Technology (AMT) program, where Intel demonstrated next-generation DRAM bonding techniques. While the SoftBank side hasn’t laid out every detail about how ZAM will be positioned in the market, the concept aligns closely with Intel’s previously shown direction: a different way of stacking and connecting DRAM that’s better suited for modern AI workloads.
At the heart of the idea is the “Z-Angle” approach. Traditional stacked-memory designs typically route connections straight through the stack. ZAM is expected to use a staggered interconnect topology that routes signals diagonally through the die stack instead. That change may sound subtle, but it can have major implications—especially for AI servers where power efficiency, thermals, and memory bandwidth constraints directly shape performance and operating cost.
This Z-Angle routing is intended to free up more usable silicon area for actual memory cells, helping increase density and potentially reducing thermal resistance. The bonding method could also move beyond conventional stacking by using copper-to-copper hybrid bonding, which can fuse layers more efficiently and create something closer to a single, monolithic silicon block rather than a set of distinct stacked layers.
ZAM is also described as a capacitor-less design, and Intel is expected to rely on its EMIB packaging technology to connect the memory to AI accelerators. The overall goal is to deliver a memory architecture that better matches the needs of AI training and inference, where current standards can struggle to balance performance per watt with scaling limits.
Although concrete head-to-head benchmarks aren’t being shared yet, the claimed advantages paint a clear picture of what Intel and its partner are aiming for versus today’s popular high-bandwidth memory solutions. Expectations being discussed include 40–50% lower power consumption, simplified manufacturing enabled by the Z-Angle interconnect strategy, and dramatically higher capacity per chip—potentially up to 512GB.
For SoftBank, collaborating on ZAM could mean more than just access to a new memory technology. It could also bring tighter control over an entire memory stack that could later pair with custom AI silicon. That combination would allow more freedom in architectural design choices and better end-to-end optimization, especially in systems built around custom ASICs.
This isn’t Intel’s first encounter with DRAM. The company previously operated in the DRAM business but exited in 1985 after losing share amid intense competition. The stakes are different now. The AI boom has turned memory into a strategic resource, and the ability to deliver higher density with lower power has become a massive competitive advantage in data centers.
Whether ZAM becomes a true industry force will depend on how well it scales, how quickly it can be manufactured at meaningful volume, and—most importantly—whether major AI hardware players decide it’s worth adopting. If Intel can demonstrate clear benefits in efficiency and capacity and persuade top-tier accelerator vendors to integrate it, ZAM could emerge as a compelling alternative in the next wave of AI-focused memory innovation.
