High Bandwidth Memory is about to take another major leap. While the AI hardware world is getting ready for GPUs and accelerators built around HBM4—expected to power upcoming platforms like NVIDIA’s Vera Rubin line and AMD’s Instinct MI450 series—the industry is already deep into the next steps: HBM5 and HBM6. These future memory standards are being engineered to deliver more bandwidth, bigger stack capacities, and new packaging and cooling approaches designed for the brutal power demands of next-generation AI compute.
A key piece of that roadmap is new manufacturing equipment. Korean semiconductor firm Hanmi is preparing to showcase what’s being described as the first “Wide TC Bonder” equipment designed for upcoming HBM5 and HBM6 production. This system is expected to appear at Semicon Korea 2026 and is positioned as an alternative to Hybrid Bonder (HB) tools for mass production of stacked HBM.
Why does this matter? Hybrid bonding has faced technical hurdles that reportedly caused delays, and memory makers are eager for production-ready solutions that can scale quickly as demand keeps surging. The Wide TC Bonder is being highlighted as a way to improve yield not only for future memory like HBM5 and HBM6, but also for nearer-term generations including HBM4 and HBM4E. Along with yield improvements, it’s aimed at boosting overall quality and completeness through more precise bonding.
One of the most interesting technical notes is support for fluxless bonding. In simple terms, this helps reduce the oxide layer on the chip surface without relying on flux, which can improve bond strength. At the same time, it can contribute to thinner overall HBM stacks—an important advantage as stacks get taller, hotter, and harder to cool.
HBM5: built for a new class of AI platforms
HBM5 is shaping up as a substantial step up in bandwidth and stack configuration. Specifications point to an 8 Gbps data rate for the standard (non-“E”) version while increasing the total I/O to 4096 bits. That combination pushes bandwidth to around 4 TB/s per stack. The baseline stack height is expected to move to 16-Hi, and with 40 Gb DRAM dies, capacity could scale to about 80 GB per stack.
Power is where things get especially intense. HBM5 is expected to reach roughly 100W per stack, which is why advanced cooling methods are being discussed right alongside performance targets. HBM5 packaging and platform concepts also point to deeper integration at the base die level and platform-level memory system design enhancements.
HBM5 feature snapshot (as described in current targets)
Data rate: 8 Gbps
I/Os: 4096
Bandwidth: 4.0 TB/s per stack
Stack height: 16-Hi baseline
DRAM die capacity: 40 Gb
Capacity per stack: up to 80 GB
Power per stack: around 100W
Packaging method: Microbump (MR-MUF)
Cooling approaches mentioned: immersion cooling, thermal via (TTV), thermal bonding
Additional concepts: dedicated decoupling capacitor die stack, custom HBM base die with 3D NMC-HBM and stacked cache, LPDDR + CXL in base die
Platform mentions: NVIDIA Feynman and AMD Instinct MI500 era designs
HBM6: doubling bandwidth and pushing stacks higher
HBM6 is where the roadmap starts to look truly extreme. The headline jump is bandwidth: targets indicate 8 TB/s per stack, effectively doubling HBM5. Data rate climbs to 16 Gbps while keeping the I/O count at 4096. DRAM die capacities are projected around 48 Gb, and stacking may go beyond today’s common limits—moving past 16-Hi into 20-Hi stacks.
That translates into much larger capacities per stack, landing in the 96 GB to 120 GB range depending on the stack configuration. Unsurprisingly, power rises again too, with projections around 120W per stack. To support these requirements, HBM6 is expected to adopt new bonding methods and more advanced packaging architectures, including a shift toward bump-less copper-to-copper direct bonding.
HBM6 feature snapshot (as described in current targets)
Data rate: 16 Gbps
I/Os: 4096
Bandwidth: 8.0 TB/s per stack
Stack height: 16-Hi / 20-Hi
DRAM die capacity: 48 Gb
Capacity per stack: 96 GB / 120 GB
Power per stack: around 120W
Packaging method: bump-less Cu-Cu direct bonding
Cooling approach: immersion cooling
Advanced concepts under discussion: custom multi-tower HBM designs, active/hybrid (silicon + glass) interposer approaches, and research-stage additions like onboard network switch, bridge die, and asymmetric TSV
HBM4 arrives first, but the next wave is already in motion
HBM4 is expected to enter mass production this year, setting the stage for the next generation of AI accelerators. But the rapid pace of AI infrastructure buildouts means HBM5 and HBM6 development is being prepared in parallel. These standards promise major bandwidth gains and new manufacturing and cooling innovations—exactly what’s needed as GPUs and AI accelerators continue scaling up in compute density, memory capacity, and power.
The takeaway is clear: HBM isn’t just getting faster. The entire ecosystem—bonding equipment, packaging techniques, interposers, and cooling—is evolving to make these gigantic memory stacks manufacturable at high yield and reliable at extreme power levels.
