AMD EPYC Venice CPUs with Zen 6 set for July reveal, bringing up to 256 cores and next-gen server performance
AMD is preparing to unveil one of its most important server processor families yet. The company’s next-generation EPYC “Venice” CPUs, built on the upcoming Zen 6 architecture, are set to be introduced during AMD’s Advancing AI event on July 22 and 23.
The confirmation came from AMD CTO and Executive Vice President Mark Papermaster, who said the new EPYC platform will continue AMD’s push for leadership in x86 server performance. According to Papermaster, enterprise customers remain deeply invested in x86 infrastructure, with decades of software, workloads, and deployment experience tied to the platform. AMD’s goal with Zen 6 is to keep improving that foundation while preparing data centers for the growing demands of AI, cloud computing, and traditional enterprise workloads.
EPYC Venice will represent AMD’s sixth generation of Zen-based server processors. Since the first Zen launch in 2017, AMD has steadily expanded its server CPU portfolio, gaining major ground in high-performance computing, enterprise infrastructure, and hyperscale data centers. With Venice, AMD appears ready to push core counts, bandwidth, and platform capabilities even further.
One of the biggest highlights of EPYC Venice is its expected jump in core count. The flagship Zen 6 EPYC CPU is expected to feature up to 256 cores, a major increase over the current EPYC Turin lineup, which tops out at 192 cores. That would mark a 33% increase in maximum core count, making Venice a powerful option for heavily threaded workloads such as virtualization, cloud services, large databases, scientific computing, rendering, and AI-related infrastructure tasks.
AMD has also indicated that EPYC Venice is designed to deliver more than 70% higher performance and efficiency compared with the Zen 5-based generation. If that claim holds across real-world workloads, it could make Zen 6 one of AMD’s most significant server upgrades in years.
Another major milestone is manufacturing. EPYC Venice has already entered production using TSMC’s advanced 2nm process technology. This makes it one of the first high-performance computing processors to move into production on the cutting-edge node. AMD has said production is ramping in Taiwan, with future manufacturing also planned for TSMC’s Arizona facility.
The Zen 6 EPYC platform is also expected to move to a new SP7 socket. Alongside the new socket, Venice will support 16-channel memory, offering up to 1.6 TB/s of memory bandwidth. That kind of bandwidth will be especially important for data-heavy workloads, including analytics, AI training support, high-performance databases, and large-scale enterprise applications.
PCIe 6.0 support is another key upgrade. The new standard should improve data movement between CPUs, GPUs, networking hardware, storage devices, and AI accelerators. As modern servers increasingly rely on fast CPU-to-GPU communication, especially in AI and accelerated computing environments, PCIe 6.0 could help reduce bottlenecks and improve overall system efficiency.
While EPYC Venice is aimed at servers and enterprise deployments, mainstream consumer Zen 6 processors are not expected to arrive soon. AMD is likely to focus first on the data center market, where demand for faster and more efficient x86 CPUs remains strong. Desktop and laptop Zen 6 chips may not appear until much later, with a possible introduction around CES 2027.
The upcoming reveal on July 22 and 23 should provide a clearer look at AMD’s next server roadmap, including performance targets, platform details, and how Venice will fit into the company’s broader AI and enterprise strategy. With up to 256 cores, 2nm production, PCIe 6.0, massive memory bandwidth, and a focus on x86 workload leadership, AMD EPYC Venice could become one of the most important server CPU launches in the company’s history.
