AMD EPYC Venice Zen 6 CPU showcased with up to 256 cores for next-generation AI data centers
AMD has given the data center world a major preview of its next-generation EPYC Venice processor, and the headline feature is hard to ignore: up to 256 Zen 6 cores and 512 threads in a single server CPU.
The chip was showcased around AMD’s Advancing AI event in San Francisco, where promotional displays highlighted what appears to be the flagship EPYC Venice design. Built for the next wave of high-performance computing and AI infrastructure, Venice is positioned as AMD’s 6th Gen EPYC platform and one of the company’s most ambitious server CPU launches to date.
While GPUs continue to dominate AI training headlines, CPUs are becoming increasingly important in modern data centers. Agentic AI, reinforcement learning workflows, data orchestration, inference pipelines, and large-scale enterprise automation all require powerful general-purpose processing. These workloads depend not only on raw parallelism but also on strong single-threaded performance, memory bandwidth, I/O capability, and platform efficiency.
That is exactly where AMD wants EPYC Venice to stand out.
The upcoming EPYC Venice family is based on the new Zen 6 CPU architecture and is expected to use TSMC’s advanced 2nm process technology. This makes the chip especially important for high-performance computing customers, as the move to 2nm brings a major transistor-level upgrade. TSMC’s 2nm node shifts from FinFET to nanosheet gate-all-around transistor technology, which is designed to improve performance, reduce power consumption, and increase transistor density.
According to the figures associated with the process, the 2nm technology can deliver around 10% to 15% higher performance at the same power, 25% to 30% lower power usage at the same performance, and up to 15% better transistor density. For large data centers, those gains can translate into better performance per rack, lower energy costs, and improved total cost of ownership.
The flagship AMD EPYC Venice processor is described as a massive chiplet-based design. It reportedly features eight large compute dies, with each compute die carrying 32 Zen 6 cores. Each of those dies is split into two 16-core complexes, giving the full processor a total of 256 cores. With simultaneous multithreading, that means up to 512 threads.
In addition to the compute dies, the chip includes two large I/O dies positioned at the center of the package. These I/O dies are expected to handle a broad range of data center connectivity features, including PCIe 6.0, UCIe, DDR5 memory support, and other platform controllers. This kind of I/O capability is essential for AI servers, where CPUs must feed accelerators, storage, networking hardware, and memory subsystems without becoming a bottleneck.
AMD has suggested that EPYC Venice can deliver more than a 70% improvement in performance and efficiency, along with a more than 30% increase in thread density. Those numbers point to a significant generational jump over current EPYC platforms and show how aggressively AMD is scaling its server roadmap for AI-era computing.
The EPYC Venice processors are also expected to play a major role in AMD’s Helios AI rack platform. These systems are designed for dense AI infrastructure, where CPUs, GPUs, memory, and networking must work together as a unified platform. In this environment, a high-core-count Zen 6 EPYC CPU can provide the control, scheduling, data handling, and sustained throughput needed to keep AI workloads running efficiently.
Competition in this market is heating up quickly. NVIDIA is pushing its own CPU strategy with Vera processors for future AI rack systems, while AMD is relying on the strength of EPYC, Zen 6, and its broader accelerator ecosystem. AMD claims its current 5th Gen EPYC Turin processors already perform strongly in early comparisons, while the upcoming Zen 6-based Venice chips are expected to push performance further with better efficiency and stronger overall value at similar power levels.
The need for more capable server CPUs is growing as AI workloads become more complex. Agentic AI systems do not simply run one large model in isolation. They often involve many connected tasks, including reasoning loops, tool usage, memory retrieval, database interaction, code execution, planning, and real-time decision-making. These workloads can place heavy demands on CPU resources, especially when scaled across enterprise environments.
That makes the AMD EPYC Venice launch especially important. With up to 256 cores, next-generation Zen 6 architecture, 2nm manufacturing, PCIe 6.0 support, high-speed DDR5 memory capability, and a platform designed for AI racks, Venice is shaping up to be one of AMD’s most powerful server CPU families yet.
If AMD delivers on its performance and efficiency claims, EPYC Venice could become a key processor for hyperscale data centers, AI cloud platforms, enterprise servers, high-performance computing clusters, and next-generation infrastructure built around autonomous AI workloads.
The official launch is expected in 2026, and all signs point to AMD preparing a major leap for the EPYC lineup. For data centers looking beyond traditional CPU performance and toward AI-optimized infrastructure, AMD EPYC Venice may be one of the most important server processors to watch.
