A person wearing gloves holds a TensorDyne TDN AIP chip, with visible circuitry and labeled sections.

Tensordyne’s 3nm Napier AI Chip Claims 13x Blackwell Speed and 1,000 Tokens/s on Trillion-Scale Models

Tensordyne Napier AI Chip Targets NVIDIA Blackwell and Rubin With Higher AI Inference Efficiency

US-based AI company Tensordyne has announced the successful tape-out of its new Napier AI chip, a processor designed to push AI inference performance far beyond today’s leading data center accelerators. The company claims Napier can deliver significantly higher token throughput and much better power efficiency than NVIDIA’s Blackwell platform, while also challenging the upcoming Rubin generation in large-scale AI deployments.

The Napier chip is set to become the foundation of the Tensordyne Napier TDN system, an AI infrastructure platform developed in collaboration with Broadcom and HPE Juniper Networks. Rather than focusing only on raw compute power, Tensordyne is taking a broader approach that combines new AI math, tightly integrated memory, and a fast scale-up interconnect to improve the way large AI models are served in real-world data centers.

Built on TSMC’s 3nm process, Napier has now completed tape-out, meaning the chip design has moved into the manufacturing stage. This is a major milestone for Tensordyne as it prepares for beta deployments and a wider infrastructure rollout. According to the company, forecasted demand for Napier-based systems has already exceeded $200 million, with AI inference as the central target market.

AI inference has become one of the most important challenges in the industry. While training large models gets much of the attention, inference is where AI systems are used at scale by businesses, developers, and end users. Every chatbot response, AI search result, coding assistant output, image generation request, and enterprise AI query requires inference performance. As usage grows, data centers face a serious problem: delivering more tokens per second without overwhelming power and cooling budgets.

Tensordyne argues that current AI infrastructure is increasingly limited by energy consumption. Expanding power delivery and cooling capacity can be extremely expensive, and in large AI deployments, power and cooling infrastructure can account for a major portion of total costs. Instead of simply adding more accelerators and more racks, Tensordyne says Napier is designed to improve efficiency across the full AI inference stack.

At the heart of the Napier platform is TDN Math, Tensordyne’s logarithmic mathematics approach. The company says this method replaces large-scale multiplication-heavy operations with simplified addition-based computation. Since multiplication is one of the most power-hungry and performance-sensitive operations in AI workloads, reducing reliance on it could improve performance per watt, especially when running frontier AI models at scale.

The second major component is the TDN AIP, or Artificial Intelligence Processor. Each Napier processor combines substantial fast SRAM with high-bandwidth memory, aiming to keep compute units busy and reduce the time processors spend waiting for data. Memory bottlenecks are one of the biggest barriers to efficient AI inference, particularly for very large models that require enormous amounts of data movement. By placing fast memory closer to compute resources and pairing it with HBM, Tensordyne hopes to improve utilization and reduce wasted cycles.

The third pillar is TDN Link, the company’s any-to-any scale-up interconnect. This proprietary fabric is designed to deliver sub-microsecond communication latency between processors. In AI inference, especially with large models split across multiple chips, fast communication is essential. If accelerators spend too much time waiting for data from neighboring chips, overall throughput falls. Tensordyne says TDN Link is built to minimize those bottlenecks and allow Napier processors to work together more efficiently.

These technologies come together in the Tensordyne TDN72 Inference Pod and Rack system. Each pod contains 72 Napier AI chips, positioning it directly against rack-scale accelerator systems built around NVIDIA’s Blackwell and future Rubin GPUs. Tensordyne claims its Napier rack can deliver major gains in AI inference performance while requiring less supporting infrastructure.

According to Tensordyne’s figures, a Napier rack can provide 17 times more tokens per watt compared with NVIDIA Blackwell and 13 times more tokens per second. The company also claims the improved efficiency and throughput could generate up to $33 million more annual revenue per rack, depending on deployment model and workload.

The comparison becomes even more aggressive when Tensordyne looks ahead to NVIDIA Rubin. The company says Napier can support multi-trillion-parameter models with throughput of 1,000 tokens per second per user in a single-rack configuration. Tensordyne claims achieving similar performance with competing infrastructure would require multiple racks based on Rubin and additional accelerator systems.

If these claims hold up in real-world deployments, Napier could represent a major shift in AI inference economics. The AI industry is currently racing to solve the power, space, and cost problems created by rapid adoption of large language models and generative AI tools. More efficient inference hardware could help cloud providers, AI labs, and enterprises serve more users with fewer racks, lower energy use, and reduced cooling demands.

However, the chip still has to prove itself outside company projections. Tape-out is an important step, but production silicon, software maturity, workload compatibility, and large-scale deployment performance will determine whether Napier can truly compete with established AI platforms. NVIDIA’s advantage is not only hardware; it also includes a mature software ecosystem, developer tools, libraries, and deep integration across the AI industry. For any new AI chip company, matching performance is only part of the challenge.

Even so, Tensordyne’s approach is notable because it targets the full inference pipeline rather than only chasing peak compute numbers. By combining logarithmic AI math, memory-focused processor design, and low-latency chip-to-chip communication, Napier is designed to attack the key pain points facing modern AI data centers.

The company’s message is clear: future AI infrastructure cannot scale efficiently by consuming more power and adding more racks indefinitely. If Napier delivers the promised gains in tokens per watt and tokens per second, it could become a serious contender in the next generation of AI inference hardware.

For now, Tensordyne’s Napier chip stands as one of the more ambitious attempts to challenge NVIDIA’s dominance in AI acceleration. With production underway and beta deployment plans moving forward, the industry will be watching closely to see whether Napier can turn its bold performance claims into real-world results.