Synopsys, a prominent player in the electronic design automation (EDA) space, has officially received certification for its AI-driven digital and analog design flows on Samsung Foundry’s advanced SF2 process. This benchmark achievement comes with the announcement of their strategic collaboration focusing on design flows, multi-die integrations, and process readiness at the cutting-edge SF2/SF2Z nodes.
The digital and analog design flows, powered by Synopsys’ comprehensive EDA suite, Synopsys.ai, are set to enhance power, performance, and area (PPA) outcomes, elevate productivity levels, and streamline the transition of analog designs to Samsung Foundry’s latest Gate-All-Around (GAA) technology stack. Leveraging AI-driven design technology and co-optimization solutions, significant improvements in performance and power efficiency were achieved, demonstrating superior results compared to non-AI augmented methods. Building on this success, Samsung will extend these optimization techniques to its advanced SF1.4 process.
The certified design flows have been substantiated by testing multiple chip tape-outs, underscoring the readiness of digital and analog processing for the SF2/SF2Z process series. Advancements include the development of backside power delivery and nanosheet optimization for more effective power distribution. Moreover, Synopsys’ IP portfolio, silicon proven on the SF2 process, is strategically positioned to lower integration risks and hasten silicon projects to fruition. The collaboration has also yielded a robust multi-die design reference flow and Universal Chiplet Interconnect Express (UCIe) IP tailored for the SF2 process, propelling 2.5D and 3D heterogeneous integrations.
As part of the collaboration on AI-integrated EDA flows, Synopsys has introduced a novel analog design migration reference flow. This allows for efficient migration of Samsung’s 8nm analog IPs to the SF2 process with Synopsys ASO.ai – another AI-driven design prowess focusing on expedited analog design transfers. This enhancement dovetails with Synopsys’ established flows, previously successfully executed on Samsung’s 14nm to 8nm/SF5 processes.
Synopsys continues to pave the way with new design strategies and methodologies apt for advanced GAA processes. Customers stand to benefit from designs featuring backside routing, local layout effect-aware methodologies, and tailored nanosheet cell designs conducive to achieving desired power, performance, and area targets on the Samsung SF2 process family. The integration of novel routing approaches and super-cell concepts via Synopsys’ tools can potentially elevate transistor performance efficiency and density, optimize power consumption, and reduce area footprint by up to 20% for SF2Z process technology implementations.
Synopsys’ vast IP portfolio aligns with Samsung’s standard and automotive-grade processes, spanning from SF2 to SF14LPU. This unleashes a competitive edge for chip manufacturers to minimize integration risks and hasten time-to-market. The comprehensive set includes industry-compliant, time-tested interface IP for Samsung’s processes, supporting PCIe, DDR5, LPDDR variants, MIPI M-PHY, USB standards, and DisplayPort for extensive protocol interoperability. Additionally, Synopsys UCIe IP success stories span multiple SF process nodes, promising efficient die-to-die connectivity with optimized power and latency metrics. Synopsys Foundation IP exceeds industry benchmarks, delivering top-tier power, performance, and area in a multitude of Samsung process technologies.
Stimulating next-generation multi-die designs, customers can engage with Synopsys 3DIC Compiler, a cohesive platform from design exploration to sign-off, specifically honed for 2.5D and 3D heterogeneous integrations and sophisticated packaging solutions. Having secured qualification for the SF2 process, the Synopsys 3DIC Compiler fully supports Samsung’s advanced silicon processes, packaging technologies, and 3DCODE standards. Synopsys reinforces this ecosystem as an active contributor to the Samsung Foundries’ MDI Alliance, ensuring customers experience seamless transitions to more intricate packaging design strategies.
