SMIC, China’s largest contract chipmaker, is reportedly turning its attention to advanced chip packaging as the semiconductor industry finds new ways to raise performance beyond the traditional pace of Moore’s Law. With leading players using cutting-edge packaging methods to squeeze more power and efficiency out of existing process nodes, SMIC appears eager to build a stronger position in the “back end” of chip production—where packaging and testing can be just as important as transistor size.
Recent reports indicate SMIC is setting up a dedicated research organization in Shanghai focused on advanced packaging technologies. The goal is to develop key capabilities that help link wafer manufacturing more tightly with packaging and testing, creating an improved pipeline from production to finished high-performance chips. This kind of coordination matters because modern chip performance gains increasingly come from how multiple dies are connected and integrated, not only from shrinking transistors.
This isn’t SMIC’s first step into packaging work. The company has previously been associated with cooperative efforts in the packaging ecosystem, including work that aligns with more established packaging and testing services. However, its existing packaging portfolio is said to be centered on more conventional approaches, such as wafer bumping, wafer-level packaging (WLP), chip-scale packaging (CSP), traditional packages, and testing services. Those methods are important building blocks, but they don’t fully match the latest 2.5D and 3D packaging technologies that are now in high demand for high-performance computing and AI workloads.
A major takeaway is that SMIC reportedly lacks a widely competitive 2.5D/3D packaging solution comparable to the advanced platforms used by the industry’s best-known leaders. Developing that capability is not a quick switch to flip. Advanced packaging typically requires extremely precise manufacturing equipment, high-quality interposers and substrates, tight process control, and an experienced supply chain that can deliver consistent yields at scale.
The timing also makes sense from a market perspective. Advanced packaging capacity has become a bottleneck globally, with demand fueled by AI accelerators, data center processors, and other performance-hungry applications. As supply constraints persist and customers hunt for alternatives, investment in packaging R&D becomes harder for any major foundry to ignore.
For China’s broader semiconductor ambitions, advanced packaging could be especially strategic. If progress on leading-edge transistor scaling remains constrained, packaging innovation offers another route to push real-world performance higher—by improving bandwidth, reducing power loss in interconnects, and enabling larger “systems in package” that combine multiple chiplets. It may not deliver immediate breakthroughs on its own, but it can be a meaningful lever over time, particularly as chiplet-based design becomes more common across the industry.
In short, SMIC’s move toward a dedicated advanced packaging research effort signals a recognition of where chip innovation is headed: not just smaller transistors, but smarter integration. If SMIC can strengthen coordination between wafer manufacturing and packaging/testing—while deepening collaboration with external OSAT partners—it could gradually build a more competitive foundation in an area that is increasingly central to modern chip performance.
