Samsung is reportedly taking DRAM manufacturing into truly single-digit nanometer territory, producing what’s being described as the world’s first “standalone” DRAM working die made on a process technology below the traditional 10nm class. If the early results hold up, this could mark a major turning point for memory density, power efficiency, and the pace of future DRAM scaling—especially as AI workloads continue to push demand for faster, larger memory pools.
For years, the DRAM industry has stretched “10nm-class” production across multiple refinements (often referred to as 1x, 1y, 1z, 1a, 1b, 1c, and 1d). While these nodes improved performance and density, they largely stayed within the same broad generation. Now Samsung is reportedly developing a new DRAM process labeled 10a that effectively moves below the 10nm threshold.
Industry sources say Samsung recently confirmed a working die after manufacturing wafers using this 10a process and then evaluating die characteristics. The next big goal is yield—turning a working result into a stable, repeatable, high-volume manufacturing process. Samsung is reportedly expected to pursue yield improvements quickly by fine-tuning process conditions based on what it learned from the functioning die.
What makes 10a especially interesting is the reported scale: analysis suggests it could shrink feature sizes down to roughly 9.5–9.7nm, which would make it the first sub-10nm DRAM process technology in the industry. Two key technology shifts are credited for enabling this step: a new 4F square cell structure and a Vertical Channel Transistor (VCT) process.
The cell structure change is a big deal for DRAM density. Many current DRAM designs use a 6F structure arranged like a rectangular 3F x 2F block. Moving to a 4F design makes the cell layout more square at 2F x 2F. That seemingly simple geometric change can translate into substantial gains: estimates suggest DRAM makers can boost cell density per integrated circuit by around 30% to 50% just by adopting the 4F structure. Higher density can mean more capacity in the same physical footprint, and it can also contribute to power savings—important for everything from smartphones and laptops to data center accelerators.
Samsung’s reported plans don’t stop at 10a. The 4F-based approach is expected to debut with 10a and then be refined further in later generations like 10b and 10c. After that, the roadmap reportedly points to an even bigger shift: 10d DRAM is expected to transition to 3D DRAM technology, with timing suggested around 2029–2030.
Materials are also part of the story. The upcoming DRAM is said to use newer materials such as Indium Gallium Zinc Oxide (IGZO), rather than relying solely on silicon as previous generations did. As DRAM cells become narrower and harder to manage, leakage and retention become more challenging. IGZO is associated with lower leakage in these tighter structures, which can help preserve data retention—an increasingly critical factor as scaling continues.
Competitive dynamics around next-generation DRAM are intensifying. Some competitors are reportedly holding off on adopting 4F, choosing instead to wait and focus on 3D DRAM as the next major leap. At the same time, manufacturers that lack access to cutting-edge lithography equipment may find it harder to keep pace with advanced DRAM scaling—though there’s speculation that if 3D DRAM ends up sharing conceptual similarities with the design direction of 3D NAND, it could offer alternative pathways to progress.
One thing is clear: memory technology is again becoming a central battleground as AI growth accelerates. Training and inference workloads are pushing demand for higher bandwidth, greater capacity, and better efficiency. Developments like sub-10nm DRAM, 4F cell architectures, VCT processes, and new channel materials are all part of the industry’s effort to deliver denser, more power-efficient DRAM at scale.
Samsung is reportedly aiming to complete development of its 10a DRAM approach this year, with mass production currently projected for 2028. If that timeline holds, the next few years will be crucial—less about whether sub-10nm DRAM is possible, and more about whether it can be manufactured reliably, economically, and in the enormous volumes modern computing demands.
