Samsung Electronics is reportedly reshaping its next-generation DRAM strategy as the race for smaller, faster, and more power-efficient memory chips intensifies. The company is said to have updated its roadmap for its first sub-10nm DRAM generation, known as D0a, with a major architectural shift at the center of the plan.
According to the reported update, Samsung now intends to make wafer-to-wafer hybrid bonding the baseline structure for its D0a DRAM process. This marks a significant step for the company as it prepares for more advanced memory production beyond the 10nm class.
Hybrid bonding is becoming increasingly important in advanced semiconductor manufacturing because it allows chips or wafers to be connected more directly and efficiently. Compared with traditional packaging and interconnect methods, hybrid bonding can help improve performance, reduce power consumption, and enable higher density. For DRAM, where scaling has become more difficult with each new generation, this kind of technology could play a key role in extending progress.
The change also suggests that Samsung is separating its vertical-channel-transistor, or VCT, design from the standard D0a process. Instead of making VCT the primary approach for the first sub-10nm DRAM node, the company has reportedly moved it to a separate process called D0a-V. This could give Samsung more flexibility, allowing it to advance hybrid bonding for near-term production while continuing to develop VCT technology as a more specialized or later-stage option.
This roadmap revision highlights the technical challenges facing the DRAM industry. As memory manufacturers push below 10nm, traditional scaling becomes harder due to limits in transistor design, electrical interference, heat, and manufacturing complexity. To keep increasing capacity and performance, companies are turning to new structures, advanced bonding techniques, and more complex chip architectures.
For Samsung, the reported shift could be an important move in its competition with other major memory makers. DRAM remains a critical component in smartphones, PCs, servers, AI systems, data centers, and high-performance computing platforms. Demand for faster and more efficient memory is especially strong as artificial intelligence workloads continue to grow, requiring massive amounts of bandwidth and capacity.
By making wafer-to-wafer hybrid bonding central to its D0a process, Samsung may be positioning itself to deliver next-generation DRAM with better speed, efficiency, and scalability. At the same time, keeping VCT development on a separate track may allow the company to refine that technology without delaying the broader rollout of its first sub-10nm DRAM platform.
While Samsung has not officially detailed the full roadmap publicly, the reported adjustment points to a broader industry trend: the future of DRAM will depend not only on shrinking process nodes, but also on new ways of stacking, connecting, and designing memory at the structural level.
If successful, Samsung’s revised D0a strategy could strengthen its position in the advanced memory market and help shape the direction of sub-10nm DRAM manufacturing in the years ahead.
