PCI-SIG has taken the next big step toward the future of high-speed expansion with the PCI Express 8.0 specification. A new 0.5 draft is now available for member review, outlining a massive jump in throughput that targets the needs of next-generation data centers and other data-hungry computing markets. PCI-SIG says the full PCIe 8.0 standard remains on schedule for release by 2028.
At the heart of PCIe 8.0 is a dramatic bandwidth leap over today’s widely deployed standards. The spec is designed to deliver a 256 GT/s raw data rate and up to 1 TB/s of raw bi-directional bandwidth when using a full x16 lane configuration. That’s a huge uplift in interconnect capacity and is positioned as an eightfold increase in raw data rate and bandwidth compared to PCIe 5.0, helping the industry keep pace with accelerating demands from AI infrastructure, advanced networking, and large-scale compute.
Like PCIe 6.0, PCIe 8.0 continues using PAM4 signaling to push more data through existing lane structures. Importantly for long-term platform stability, PCIe 8.0 is also planned to maintain backwards compatibility with previous generations of PCIe technology, which is critical for ecosystem adoption across servers, workstations, and emerging compute platforms.
PCI-SIG’s roadmap aims to double I/O bandwidth roughly every three years, and PCIe 8.0 is framed as the next milestone in that cadence. Here’s how the projected PCIe 8.0 bandwidth scales by lane count:
To put those numbers into perspective, PCIe 8.0 at x1 is expected to offer the same bandwidth as PCIe 4.0 running at x16, and it aligns with what PCIe 5.0 can do at x8. Move up to x2 and it matches the full bandwidth of PCIe 5.0 at x16. At x4, it reaches the full capability associated with PCIe 6.0-class throughput.
Beyond raw speed, PCI-SIG says PCIe 8.0 development is also focused on real-world platform challenges. The group is evaluating new connector technologies, working on protocol enhancements to improve effective bandwidth, and exploring additional techniques to reduce power. The organization also highlights the need to meet targets for latency, forward error correction (FEC), and overall reliability—areas that become even more important as signaling rates climb and systems scale out.
PCI-SIG describes PCIe 8.0 as being built for high-bandwidth, low-latency environments, specifically calling out data-intensive markets such as AI, data centers, high-speed networking, edge computing, and quantum computing. If the spec lands as planned, PCIe 8.0 could become a foundational interconnect for the next era of accelerators, storage, and networking hardware where moving data quickly is just as important as raw compute performance.
