MediaTek may be proving once again that you don’t always need the newest CPU cores to build a fast flagship-class mobile chip. With the newly revealed Dimensity 9500s, the company is leaning into a bold “all big cores” approach and pairing it with an unusually large cache configuration—an engineering move that could help offset the typical disadvantages of using slightly older CPU core designs.
A quick look at the Dimensity 9500s specs shows the headline idea clearly: an all-big-core CPU layout. The chip reportedly features one Cortex‑X925 prime core clocked up to 3.73GHz with 2MB of L2 cache, backed by three Cortex‑X4 cores (each with 1MB L2) and four Cortex‑A720 cores (each with 512KB L2). On the graphics side, it’s paired with an Immortalis‑G925 MP12 GPU with ray tracing support, positioning it as a high-end option for gaming and demanding visual workloads.
The rest of the platform details also look thoroughly modern. The Dimensity 9500s is built on TSMC’s 3nm N3E process, supports LPDDR5X memory, and uses UFS 4 storage with MCQ. MediaTek is also highlighting its NPU with “agentic AI” support, a term increasingly tied to on-device AI features that can plan, assist, and automate tasks more intelligently without constantly relying on the cloud.
What makes the Dimensity 9500s especially interesting, though, is the apparent tradeoff MediaTek is making. While the Dimensity 9500 used ARM’s latest CPU cores, the Dimensity 9500s is said to use cores that are at least one generation older. Normally, that would raise eyebrows, because newer cores typically win on both raw performance and efficiency.
Instead of following the expected playbook, MediaTek appears to be trying a different lever: cache—lots of it. The Dimensity 9500s is described as having a largest-in-class 19MB CPU cache, along with a 12MB L3 cache and 10MB of System Level Cache (SLC). Cache matters because it helps the CPU avoid reaching out to slower system memory as often. By keeping frequently used data closer to the cores, cache reduces latency and can cut power use—two factors that directly impact real-world speed, sustained performance, and battery life.
For context, Qualcomm’s Snapdragon 8 Gen 5 takes a different architectural route. It reportedly uses two high-performance third-gen Oryon cores clocked at 3.80GHz plus six medium-performance third-gen Oryon cores at 3.32GHz, with an Adreno 840 GPU (also with ray tracing). It’s built on TSMC’s 3nm N3P node, includes a Hexagon NPU with agentic AI support, and supports LPDDR5X along with UFS 4.1 storage. Cache figures mentioned for Snapdragon 8 Gen 5 include 6MB of L3 cache and 30MB of SLC—showing that both companies see cache as a major tool, even if they’re tuning the balance differently.
Of course, the big question is how this plays out in benchmarks and real devices. On paper, older cores can be a disadvantage, but an aggressive cache strategy may improve efficiency and smooth performance in everyday tasks, gaming workloads, and AI-enhanced features. It will take time for credible benchmark results to show whether MediaTek’s approach is a clever shortcut to flagship performance, a play for better sustained efficiency, or both.
If the Dimensity 9500s delivers strong results, it could signal a broader shift in mobile chip design. With memory costs and platform expenses under constant pressure, some manufacturers may find it appealing to revisit older CPU cores—then compensate with smarter cache design and modern process nodes—especially for devices that need near-flagship performance without flagship pricing. MediaTek’s experiment could end up looking less like an oddity and more like an early blueprint for the next wave of cost-efficient high performance smartphones.
