Google Reportedly Turns to Marvell for a Custom TPU Networking Chip Built on Intel 18A Technology
Google is reportedly working with Marvell on a custom networking chip designed to improve the performance and efficiency of its Tensor Processing Unit infrastructure. The move comes as artificial intelligence data centers continue to expand rapidly, placing intense pressure on networking hardware that must keep massive clusters of AI accelerators synchronized.
Modern AI data centers are no longer limited by raw compute alone. As thousands of ASICs, GPUs, and specialized CPUs work together, the speed at which data moves between chips becomes just as important as the chips themselves. Networking silicon plays a critical role in this environment by linking individual accelerators into large-scale compute clusters, helping manage congestion, reduce latency, and coordinate workloads in real time.
According to recent industry chatter, Marvell is expected to design a dedicated networking chip for Google’s TPUs. The chip is said to be manufactured using Intel’s advanced 18A or 18AP process technology, with mass production potentially beginning toward the end of 2027.
If accurate, this would mark another major step in Google’s long-term strategy to build highly optimized AI infrastructure. The company has already deployed TPUs across multiple data center regions worldwide, including dedicated AI-focused zones. As these deployments grow, the need for faster, more efficient communication between TPU clusters becomes increasingly important.
The timing of this reported project is also notable. Advanced chip manufacturing capacity remains highly competitive, especially at leading-edge nodes. By using Intel’s 18A-class process, Google could diversify its supply chain while gaining access to one of Intel’s most important next-generation fabrication technologies.
The custom Marvell networking chip is expected to be paired with Google’s upcoming Humufish TPU, also referred to as TPUv8e. In that project, Google is believed to be handling the main ASIC die design, while MediaTek is reportedly involved in I/O and back-end design work. Intel is expected to manage fabrication and advanced packaging, including EMIB-based integration.
This kind of multi-company collaboration reflects the increasing complexity of AI chip development. No single component determines performance in isolation. Compute dies, memory systems, I/O controllers, packaging technology, and networking chips all need to work together efficiently to deliver the speed and scalability required by modern AI workloads.
For Google, a custom networking chip could help reduce bottlenecks inside large TPU clusters. Lower latency and better data flow would be especially important for training and running large AI models, where delays between accelerators can reduce overall efficiency and drive up operating costs.
For Marvell, the reported deal would strengthen its position in the booming AI infrastructure market. The company has become increasingly important in custom silicon, data center networking, and high-speed connectivity, all of which are essential to the next phase of artificial intelligence computing.
If the chip reaches volume production by late 2027 as rumored, it could arrive at a crucial time for hyperscale AI data centers. Demand for AI compute is expected to keep rising, and companies such as Google are looking for every possible advantage in performance, power efficiency, and infrastructure scale.
While the details remain unofficial, the reported Google-Marvell-Intel effort points to a clear trend: the future of AI performance will depend not only on more powerful accelerators, but also on the specialized networking chips that connect them.
