Intel’s Robert Hallock Discusses Lunar Lake’s Strategy to Take on ARM Efficiency

Intel’s advancement in AI processing is set to take a significant leap with its upcoming Lunar Lake processors for laptops. Compared to its predecessor, Meteor Lake, Lunar Lake aims to offer a substantial threefold increase in AI capabilities, with up to 120 TOPS from CPU, GPU, and NPU combined. This boost in performance is achieved with a remarkable 40% reduction in package power consumption from Meteor Lake, emphasizing efficiency in performance per watt for notebooks without a corresponding increase in thermal design power (TDP).

Lunar Lake’s core configuration diverges from Meteor Lake, particularly in its approach to efficiency cores. The new Skymont E-cores in Lunar Lake provide 1.68 times more performance at the same frequency while operating at lower power. This development has led to the merging of Energy (E)-cores and Low Power (LP) E-cores into a single 4C4T E-core complex, which also serves as the low-power island in Lunar Lake. This consolidation has simplified the design while enhancing both power efficiency and computing performance.

Hyperthreading, a staple feature for improving performance in CPUs, is being set aside for Lunar Lake’s new P-cores. With the advancements in core architecture and process technologies, Intel suggests that physical cores offer superior performance, power, and area efficiency compared to Simultaneous Multithreading (SMT) threads. The decision to forgo Hyperthreading with Lunar Lake stems from a belief that physical cores better maximize performance per watt in low-power scenarios.

In terms of connectivity, Thunderbolt 4 will remain the most commonly used technology in Lunar Lake, even as Thunderbolt 5 emerges. Lunar Lake will require a minimum of two Thunderbolt 4 ports, supporting up to three. Wi-Fi 7 is also built into the Lunar Lake SoC, which means users can expect speeds up to 5.9 Gbps and an improved, more efficient design thanks to integrated components like the Digital MAC.

Regarding the production strategy, Intel has chosen to utilize TSMC’s N3B technology for the compute tile in Lunar Lake as part of its IDM 2.0 strategy. This allows for flexibility in selecting process technologies that align with product goals in terms of schedule, power, and performance. Meanwhile, assembly and packaging processes are being handled in Intel’s facilities.

In the face of the growing popularity of ARM-powered laptops, Intel maintains that the efficiency narrative between ARM and x86 architectures is misconstrued. They argue that it isn’t the instruction set architecture that broadly dictates power, but the design choices and transistor costs that determine the power consumption and TDPs of a CPU. Intel believes the design decisions in Lunar Lake, including significant improvements in the E-core and P-core architectures, optimized Thread Director capabilities, and a new low-power fabric, enable Lunar Lake to potentially surpass ARM designs in package power efficiency.

Intel’s ambition with Lunar Lake is to prove the potential for lower power consumption in x86 architecture in an era where ARM-on-Windows designs are increasing in power requirements. They are confident that the improvements and strategic choices in the Lunar Lake design will demonstrate the feasibility of high-efficiency x86 processors, casting a new light on the efficiency debate in the industry.