Fresh details about Intel’s next-generation Nova Lake processors are starting to line up with earlier rumors, and the newest leak suggests the company is shrinking its compute tile die to just under 100 mm². If accurate, that’s a noticeable step forward in silicon density and efficiency compared to the current Arrow Lake generation.
According to information shared by well-known leaker Golden Pig Upgrade (reported via @9550pro), the standard Nova Lake compute tile (the non-bLLC version) is said to measure 14.8 mm x 6.6 mm. That works out to roughly 97.68 mm², putting it below the 100 mm² mark. For context, Arrow Lake’s compute tile is believed to be around 117.2 mm², so Nova Lake would represent about a 16.7% size reduction.
What makes the smaller footprint more interesting is what Intel is reportedly packing inside. The standard Nova Lake configuration is expected to feature an 8+16 core layout using Coyote Cove performance cores and Arctic Wolf efficient cores, along with an extra set of 4 low-power efficient cores that are said to be non-overclockable. If those specs hold, Intel would be delivering more compute capability in a tighter area—exactly the kind of improvement enthusiasts watch for when a new architecture approaches.
There’s also talk of a more gaming-focused Nova Lake variant that adds a large on-die last-level cache, often described as bLLC. This is the version rumored to target competition with AMD’s X3D-style chips, which boost gaming performance by increasing cache capacity and improving memory access behavior in many titles. The leaked dimensions for the bLLC tile are 14.8 mm x 10.4 mm, or about 153.92 mm²—roughly 57% larger than the standard tile. That extra silicon won’t come cheap, either, since larger dies built on advanced manufacturing nodes (Nova Lake is rumored to use TSMC’s N2 process) typically carry higher production costs, which can translate into higher retail pricing.
On top of single-tile designs, the leak also points to higher-end Nova Lake SKUs using dual compute tiles. In that scenario, a dual standard-tile setup could reach around 195 mm² of compute tile area, while a dual bLLC configuration could balloon to roughly 307 mm² due to the added cache. The report also mentions extreme power headroom on certain dual-tile parts, with an “800+ Watts” PL4 limit referenced—though that figure, in particular, should be treated cautiously until anything official backs it up.
Here’s a quick recap of the rumored die sizes mentioned:
Intel Nova Lake 8+16 (Standard Compute Tile) = ~97.68 mm²
Intel Nova Lake 8+16 + 144 MB (bLLC Compute Tile) = ~153.92 mm²
Intel Nova Lake 16+32 (Dual Compute Tile) = ~195 mm²
Intel Nova Lake 16+32 + 288 MB (bLLC Dual Compute Tile) = ~307 mm²
For comparison, the same report includes estimates for AMD’s chiplet dies:
As always with early leaks, nothing here is confirmed, and specs like die dimensions, cache capacity, and tile configurations can shift before launch. Still, if the numbers are even close, Nova Lake looks poised to bring a meaningful die shrink over Arrow Lake while also introducing cache-heavy variants designed to chase top-tier gaming performance.
