Huawei’s newest mobile chip, the Kirin 9030, is suddenly one of the most talked-about smartphone processors—not just because it powers fresh flagship devices, but because it represents a major real-world test of how far China can push advanced chipmaking without access to the latest EUV lithography tools.
The Kirin 9030 and Kirin 9030 Pro debuted inside Huawei’s Mate 80 and Mate X7 smartphones, giving Huawei’s HiSilicon and manufacturing partner SMIC a high-profile platform to demonstrate progress under years of export restrictions that limit access to cutting-edge semiconductor equipment.
Kirin 9030 and Kirin 9030 Pro specs (based on early benchmark data)
Early benchmark listings suggest both chips rely on ARMv8 CPU designs and use the same Maleoon 935 GPU, though the reported figures appear to be preliminary and may not reflect final performance tuning.
For the standard Kirin 9030, the configuration is listed as:
– 8 ARMv8 CPU cores with 12 threads
– Prime core clocked at up to 2.75GHz
– Performance cores at around 2.27GHz
– Efficiency cores at around 1.72GHz
– Maleoon 935 GPU
For the Kirin 9030 Pro, the configuration is listed as:
– 9 ARMv8 CPU cores with 14 threads in a 1+4+4 layout
– Prime core clocked at up to 2.75GHz
– Performance cores at around 2.27GHz
– Efficiency cores at around 1.72GHz
– Maleoon 935 GPU
Because these numbers come from provisional testing, there’s a strong chance software optimization, power limits, or unfinished firmware is preventing the chips from running at their full potential in current results.
A closer look at fabrication: pushing DUV to the edge
A teardown of a Mate 80 Pro Max has provided more insight into what makes the Kirin 9030 particularly interesting. The analysis indicates the chip is manufactured using SMIC’s N+3 process technology, positioned as an evolution beyond the company’s earlier N+2 second-generation 7nm-class manufacturing.
However, the N+3 process is not expected to be a direct match for “true” 5nm-class nodes produced by leading foundries elsewhere. Instead, it appears to sit somewhere between 7nm and 5nm in practical terms—an incremental step rather than a clean generational leap.
The key takeaway: rather than relying on EUV lithography, SMIC appears to be extending its existing DUV-based approach. DUV (Deep Ultraviolet) lithography uses 193nm light to pattern features on silicon wafers. To create smaller and more complex structures without EUV, manufacturers can repeat exposure and patterning multiple times, a strategy known as multi-patterning. This can achieve tighter geometries, but it becomes increasingly difficult, expensive, and sensitive to tiny errors as the complexity rises.
DTCO: improving results through design and manufacturing coordination
Another major factor highlighted in the analysis is Design Technology Co-Optimization (DTCO). Instead of treating chip design, process tuning, and yield improvement as mostly separate phases, DTCO attempts to optimize them together. When paired with heavy DUV multi-patterning, DTCO can help manage issues that grow worse at smaller scales, including edge placement errors and process variation.
In plain terms, DTCO is one way to squeeze more real performance and manufacturability out of a process that’s approaching its limits—especially when the most advanced lithography option isn’t available.
Where the improvements may be coming from: interconnects, not transistor geometry
One of the more notable conclusions from the teardown analysis is that SMIC’s N+3 progress may not come from major changes to core transistor patterning metrics like fin pitch and contacted poly pitch, which are central to Front-End-of-Line (FEOL) scaling—the part of manufacturing focused on forming the transistors themselves.
Instead, the incremental gains appear to lean more heavily on Back-End-of-Line (BEOL) work, which includes forming the interconnect layers that link transistors together. Improving BEOL can still deliver real benefits, but it also carries risk when done with DUV multi-patterning: the more patterning steps required, the more opportunities there are for alignment errors, line roughness, and defects. If alignment precision slips, yields can drop sharply.
What Kirin 9030 signals for Huawei and SMIC going forward
The Kirin 9030 is shaping up to be less about a dramatic node shrink and more about disciplined engineering—tight coordination between design and manufacturing to extract achievable gains while staying within the constraints of DUV-based production. That approach can deliver meaningful progress, but it also has a ceiling; there’s only so much performance, power efficiency, and density that optimization can unlock when the underlying lithography is being stretched to its practical limits.
Advanced packaging could still offer another path to performance improvements in the future, but for mobile application processors like the Kirin 9030—where power, thermals, and compact integration dominate—packaging tends to be less of a headline factor than it is for larger chips.
Even with those limitations, Kirin 9030 and Kirin 9030 Pro put a spotlight on how far smartphone silicon can be pushed through multi-patterning and DTCO when EUV isn’t on the table, making Huawei’s latest Mate phones a notable milestone in the ongoing evolution of China’s semiconductor capabilities.
