Fresh chatter in the semiconductor world suggests Google may be considering Intel as a partner for its next-generation Tensor Processing Unit (TPU) chips, known internally as Humufish. Analyst Ming-Chi Kuo believes one factor will outweigh most others in Google’s decision: manufacturing yield, especially as Google increasingly prioritizes cost savings in the Humufish TPU’s design strategy.
At the center of this discussion is Intel’s advanced chip packaging approach called EMIB-T, short for Embedded Multi-die Interconnect Bridge Through Silicon Vias. In simple terms, it’s a method for connecting multiple chiplets inside a single package more efficiently and, potentially, more cheaply than some traditional approaches.
How EMIB-T differs from conventional chip packaging is a big part of why it matters. Many standard advanced packages use a silicon interposer, which helps route signals between the chip on top and the board below. Intel’s EMIB approach instead uses a small “bridge” embedded directly in the organic package substrate. That design is positioned as a way to lower costs while still supporting large, complex chip packages—exactly the type of build modern AI accelerators rely on.
EMIB-T is an evolution of this idea. It adds Through Silicon Vias (TSVs), which are vertical electrical pathways that improve conductivity by allowing current to pass more directly through the package. This addresses a key limitation of traditional EMIB, where current would otherwise need to travel around the bridge rather than taking a more direct route. For high-performance AI hardware, power delivery and signal integrity are not minor details—they can shape performance, reliability, and cost per compute unit.
Kuo’s view is that Intel’s yield progress on EMIB-T will be a deciding signal for Google. He points to a reported 90% yield as encouraging, but warns that it should be interpreted carefully. Intel’s internal target for EMIB-T is said to be closer to a 98% benchmark, referenced against established Flip Chip Ball Grid Array (FCBGA) production expectations, since EMIB is effectively an extension of FCBGA-type packaging foundations.
The gap between 90% and 98% is where things get difficult. Kuo argues that improving yields from early-stage levels up to 90% is one kind of challenge—but pushing from 90% to 98% is significantly harder, and often where advanced packaging programs face the most pressure. He also notes that the 90% figure may represent a technology validation milestone rather than true high-volume manufacturing performance. In other words, it’s promising, but not yet proof that the process is fully ready for large-scale, cost-efficient production. His takeaway: cautious optimism is the most reasonable stance until production-grade yield data becomes clearer.
Why would Google care so much about packaging yields? Because yields directly translate to cost. Higher yields generally mean more usable units per manufacturing run, less waste, and better margins—critical when competing in AI infrastructure against NVIDIA, where performance per dollar is a relentless battleground.
Kuo adds that Google’s cost focus is showing up in other ways, too. Reportedly, Google has also explored potential savings with TSMC by considering a more direct tape-out of Humufish’s primary design, instead of leaning on a partner such as MediaTek. Tape-out is the stage where a chip design is finalized and sent to a fabrication facility to begin production. A more direct route can sometimes offer better control over costs, timelines, and optimization—though it also shifts more responsibility onto the company making the decision.
For now, the story is less about a confirmed supplier switch and more about the variables that could shape Google’s next TPU generation. If Intel can demonstrate consistently high EMIB-T yields at production scale—approaching that 98% benchmark—it could strengthen Intel’s position as Google weighs performance, supply reliability, and most importantly, total cost.
