Fujitsu Monaka CPU Set for 2027 With 144 Cores, 2nm Chiplet Design, PCIe 6.0, and Major AI Performance Gains
Fujitsu is preparing its next-generation Monaka CPU for a 2027 launch, and the chip is shaping up to be one of the company’s most ambitious processors yet. Designed as the successor to the A64FX processor used in Japan’s Fugaku supercomputer, Monaka targets high-performance computing, artificial intelligence, and energy-efficient data center workloads.
The upcoming CPU will move to a modern Arm v9.3-A-based design and bring major architectural upgrades, including support for Arm SVE2, a 3D many-core chiplet layout, ultra-low-voltage operation, confidential computing features, and a large 144-core configuration.
Fujitsu is positioning Monaka as a processor built for the next era of AI and HPC. While GPUs and accelerators often get the spotlight in artificial intelligence, CPUs remain critical for orchestration, data movement, peripheral processing, and general-purpose workloads. In HPC, CPUs are still essential for high-throughput computing and precision-heavy tasks.
With Monaka, Fujitsu aims to deliver up to twice the AI performance compared to its previous generation, reduce total cost of ownership by more than 50% through ultra-low-voltage operation, and provide secure in-use data protection through confidential computing technologies.
One of the most important changes in Monaka is its 3D chiplet-based construction. Instead of building the entire processor as one large 2nm monolithic die, Fujitsu is separating key components across multiple dies to improve efficiency, cost, and manufacturing flexibility.
The main compute die uses a 2nm process and contains the CPU cores. Beneath it sits a 5nm stacked die that houses SRAM and I/O functions. This 3D integration allows Fujitsu to use the most suitable manufacturing process for each part of the chip rather than forcing everything onto the same advanced node.
The design includes three main silicon components. The core die is built using TSMC’s N2P 2nm process to maximize performance and power efficiency. The SRAM and I/O dies use TSMC’s N5 5nm process. The last-level cache is placed in the SRAM die below the CPU cores and connected through hybrid bonding, while the I/O is linked through a silicon interposer.
This approach reduces the total 2nm silicon area by around 30%, which should help lower production costs while maintaining strong performance. Each CPU core is said to measure about 1.47 mm².
Thermal management also plays a major role in the design. Fujitsu places the core die on top because it generates the most heat, shortening the path between the hottest part of the processor and the cooling solution. The face-to-face hybrid bonding between dies also shortens signal paths, helping reduce latency. Monaka will also support per-core voltage and frequency control through an LDO system, enabling more precise power management.
Monaka will feature 144 CPU cores in a single processor. At the platform level, a dual-socket node will support up to 288 cores. The chip will also include 96 PCIe 6.0 lanes with CXL 3.0 support, giving it high-speed connectivity for accelerators, storage, networking, and memory expansion devices.
Memory support is another major highlight. Monaka is expected to support 12 channels of DDR5 memory running at speeds above 8000 MT/s. That wide memory interface should provide the bandwidth needed for AI, simulation, scientific workloads, analytics, and other data-intensive applications.
The CPU will support both liquid cooling and air cooling depending on the model. Fujitsu is preparing two main versions: a high-performance model and a high-efficiency model.
The high-performance Monaka SKU will feature 144 cores, a 2.9 GHz base frequency, and a 500W TDP. It is rated at 6013 GFLOPs in DGEMM performance and 96.2 TOPS in INT8 performance at base clock speeds. This version is designed for liquid-cooled systems where maximum performance is the priority.
The high-efficiency SKU keeps the same 144-core configuration but runs at a 2.1 GHz base frequency with a lower 350W TDP. It delivers 4355 GFLOPs in DGEMM and 69.7 TOPS in INT8 performance at base clocks. This model is intended for air-cooled deployments where power efficiency and operating cost are more important.
Monaka’s custom CPU core is optimized for AI and HPC workloads. Its enhanced SVE2 engine includes two 256-bit execution units and two 256-bit load/store units. The architecture also supports additional data types such as FP8 and INT8MM, which are especially useful for AI inference workloads.
For general-purpose performance, the core includes advanced three-level TAGE-based branch prediction and six ALUs. Reliability, availability, and serviceability features are also built in, including ECC protection in L1 and L2 caches, parity checks in execution units and registers, and a hardware instruction retry mechanism to recover from transient errors.
Fujitsu is also giving Monaka flexible NUMA configuration options to better match different software and workload needs. The processor can be configured as eight NUMA nodes with 18 cores each for last-level cache latency and throughput optimization, four NUMA nodes with 36 cores each for a balance of memory latency and throughput, or a single 144-core NUMA node for large-memory applications.
This flexibility could make Monaka useful across a wide range of deployments, from traditional supercomputing systems to AI infrastructure, cloud servers, scientific research platforms, and enterprise data centers.
Fujitsu is already sampling Monaka, with production shipments planned for 2027. The chip represents a major step forward from A64FX, combining Arm v9.3-A technology, 2nm manufacturing, 3D chiplet stacking, high core counts, fast DDR5 memory, PCIe 6.0, and CXL 3.0 into a platform built for demanding next-generation computing workloads.
Looking further ahead, Fujitsu is also working on Monaka-X, a future CPU expected around 2029. Monaka-X is planned to support SME2 for AI workloads and has been selected for the FugakuNext supercomputer project. It is also expected to integrate NVIDIA NVLink Fusion, signaling deeper connectivity between CPUs and AI/HPC accelerators in future large-scale computing systems.
