China’s DFSX Pushes Domestic AI Chip Ambitions With DF1000 Accelerator, 3D DRAM, and Infinity Chiplet Packaging
China’s AI hardware race is gaining momentum as DFSX advances a new generation of domestically built AI accelerators designed to reduce reliance on overseas memory and packaging technologies. The company has introduced the DF1000, described as China’s first 3D DRAM-powered AI accelerator developed through a domestic supply chain, alongside a future-focused 3.5D “Infinity Chiplet” architecture aimed at scaling performance for large AI models.
The DF1000 is positioned as a software-defined, near-memory computing AI accelerator built for Chinese cloud providers, AI labs, and technology companies. Rather than depending on conventional high-bandwidth memory solutions, the chip uses stacked 3D DRAM with in-memory processing capabilities, a design choice that could help address one of the biggest bottlenecks in modern AI computing: memory bandwidth.
Built on a mature 14nm process, the DF1000 delivers up to 520 TFLOPs of BF16 compute performance. While 14nm is not considered cutting-edge compared with the most advanced global semiconductor nodes, DFSX is using architectural innovation, advanced packaging, and memory stacking to extract significantly more performance from established manufacturing technology.
The standout feature is the chip’s 3D DRAM design. DFSX uses hybrid bonding to stack DRAM at the wafer level, improving memory capacity, density, and bandwidth. According to the company’s figures, the DF1000 can reach up to 6.4 TB/s of memory access bandwidth, along with 900 GB/s of scale-up interconnect bandwidth.
Hybrid bonding is important because it shrinks the interconnect pitch from micrometer levels to sub-micrometer levels. In practical terms, that means far more connections can fit into the same area, improving bandwidth density while reducing power consumption compared with traditional interconnect approaches. DFSX also claims that 3D stacking increases through-silicon vias by 10 times and can deliver five times the bandwidth at the same capacity.
This approach is being presented as an alternative to HBM, which has become essential for high-end AI GPUs but remains expensive and supply-constrained. By using 3D DRAM, DFSX aims to bypass the “HBM memory wall,” lower dependence on overseas memory supply chains, and potentially achieve a more cost-effective path to high-bandwidth AI acceleration.
The DF1000 is also designed around software-defined chip technology and near-memory computing. The goal is to bring computation closer to the memory, reducing data movement and improving energy efficiency. For large language models and AI inference workloads, this can be a major advantage because moving data often consumes more time and power than the computation itself.
DFSX says the DF1000 platform includes an independent and open software stack, toolchains, and support for distributed training and inference across mainstream large-scale AI models. The company is also offering high-performance servers with pre-installed software, designed to be compatible with major deep learning frameworks and large AI applications.
Although DFSX has not released complete independent benchmark data, its internal estimates suggest that the DF1000 can match or surpass Nvidia’s Hopper H200 in certain performance areas. The company claims the DF1000 offers twice the bandwidth of the H100 and around 33% more bandwidth than the H200. In AI model testing, the chip is said to reach 500 tokens per second on Llama 3 70B, while TPOT performance was reported at 20 ms in DeepSeek-3.2 workloads.
Beyond the DF1000, DFSX has revealed its broader strategy through the Infinity Chiplet architecture, a 3.5D+ multi-chip stacked package designed to support future AI accelerators. This architecture is built to help China’s semiconductor sector work around limitations in access to advanced process nodes and packaging technologies by making better use of mature domestic manufacturing.
The Infinity Chiplet approach focuses on three major goals. First, it uses 3.5D stacking to replace or optimize data storage structures, saving chip area while increasing bandwidth in the same physical footprint. Second, it reduces the need for HBM by relying on 3D DRAM. Third, it improves I/O power characteristics by designing the system around the absence of traditional HBM memory.
DFSX has also mapped out its next AI accelerator generations. After the DF1000, the company plans to introduce the DF2000, with production expected in the fourth quarter of 2026 and broader market availability in early 2027. The DF2000 is expected to remain on a 14nm process while delivering 1000 TFLOPs of BF16 compute, 2000 TFLOPs of FP8, and 4000 TFLOPs of FP4 performance. It is also planned to feature 15 TB/s of bandwidth through an advanced 3D DRAM design and 1600 GB/s of scale-up interconnect bandwidth.
The DF3000 is scheduled for 2028 and is designed to double the DF2000’s compute capabilities. DFSX projects 2000 TFLOPs of BF16, 4000 TFLOPs of FP8, and 8000 TFLOPs of FP4 compute, paired with 20 TB/s of bandwidth and 3200 GB/s of interconnect bandwidth. The company expects the DF2000 to reach performance levels comparable to Nvidia’s Blackwell generation, while the DF3000 is being positioned as a stronger competitor to high-end Blackwell-class AI accelerators.
The DF1000 is already being deployed in large-scale racks and POD configurations using the standard OAM 2.0 interface. A tray can include up to eight DF1000 AI accelerators, and DFSX has partnered with Zhaoxin to adapt server CPUs for the platform. A primary node is said to offer 4.16 PFLOPs of FP16 compute, 51.2 TB/s of memory bandwidth, 7200 GB/s of scale-up bandwidth, 3.2 Tbps of scale-out bandwidth, a 120-core CPU, and power consumption of around 12 kW.
Rack-scale deployments begin at 64 accelerators and can scale up to 512-accelerator hyperscale designs. This suggests DFSX is not only targeting individual AI chips but complete AI infrastructure for training and inference clusters.
The DF1000 marks an important step in China’s effort to develop a self-reliant AI hardware ecosystem. By combining 3D DRAM, near-memory computing, software-defined architecture, and 3.5D chiplet packaging, DFSX is attempting to build competitive AI accelerators without depending on the most restricted advanced manufacturing technologies.
If the company’s roadmap stays on track, the DF2000 and DF3000 could strengthen China’s domestic AI computing capabilities significantly over the next few years. The key question will be whether DFSX can deliver real-world performance, software maturity, power efficiency, and production scale at levels required by modern AI data centers.
