Cerebras is preparing a major leap in AI infrastructure with its CS-4 rack-scale system, while already laying out the roadmap for future CS-5 and CS-6 platforms. The company’s newest design is built around the WSE-3T, an upgraded version of its Wafer Scale Engine architecture, and it is aimed directly at the growing demand for faster, more efficient AI inference at massive scale.
The Cerebras CS-4 is positioned as a major upgrade over the CS-3 system. According to the company, the new rack can deliver up to twice the token generation speed and as much as 10 times better throughput per watt compared with CS-3. Since Cerebras already uses a wafer-scale chip design that is far larger than conventional AI accelerators, the CS-4 extends its existing advantage in token generation performance even further, with claims of up to a 30x lead across various AI models.
At the center of the CS-4 is the WSE-3T chip. Unlike traditional AI accelerators that rely heavily on high-bandwidth memory, Cerebras uses a massive wafer-scale design with a huge amount of on-chip SRAM. The company says a single WSE-3T chip inside CS-4 offers 43,200 TB/s of raw bandwidth. For comparison, next-generation AI chips such as NVIDIA Rubin and AMD MI455X are expected to deliver bandwidth in the range of roughly 22 TB/s to 23.3 TB/s using HBM4 memory. The comparison is not perfectly equal, because Cerebras is referring to raw on-wafer SRAM bandwidth, while the GPU figures are based on external HBM memory, but it still highlights the scale of the WSE approach.
Cerebras is integrating the WSE-3T into its new Nexus rack-scale platform. The design focuses on modularity, faster deployment, and simpler integration of power, compute, and I/O. Compared with CS-3, the CS-4 platform is intended to be easier to build, easier to service, and better suited for large AI data centers.
One of the most important changes is the use of pluggable “backpacks.” Each Nexus rack connects to modular backpacks, and each backpack contains a single WSE-3T chip. These modules combine the wafer package, cooling, power delivery, and I/O into a compact integrated unit. Cerebras says the new design uses 50% fewer components than CS-3 and is 60% automated in manufacturing, which could help improve production efficiency and deployment speed.
Power delivery is a major focus for AI infrastructure, especially as systems grow larger and more power-hungry. Traditional accelerator platforms can suffer efficiency losses because power has to travel through circuit board paths before reaching the silicon. Cerebras is trying to reduce these losses by using a 54.5V DC busbar system with no PCB between the power source and the chip. The WSE-3T sits directly on DC/DC power converters, cutting the distance between power conversion and silicon to just 0.5 mm, compared with around 50 mm in some conventional GPU-based systems. Cerebras claims this approach can provide a 100x improvement in power delivery distance efficiency.
Cooling is also integrated into each backpack. The system includes water conditioning hardware, flow regulation, leak detection, dry quick disconnects, and energy monitoring. This is designed to make installation easier while also helping operators monitor cooling performance and detect potential issues before they become serious. The cooling hardware is placed toward the rear of the backpack, while the front houses the power components.
Each backpack can include up to 30 AC/DC power supply modules, with support for up to 277VAC input and 54.5VDC output. Across a full setup, that can mean up to 90 power modules in total. These power supplies are air-cooled using dedicated fan modules, while water cooling is used for the wafer-scale compute components.
Another major advantage claimed by Cerebras is interconnect bandwidth. The CS-4 features a 53.5 PB/s fabric directly on the wafer, eliminating the need for large numbers of external cables between accelerator modules. By comparison, modern rack-scale GPU systems can require thousands of cables to connect accelerators across a rack. Cerebras says its on-wafer fabric provides up to 200 times higher fabric bandwidth than conventional GPU interconnect approaches.
The WSE-3T also includes a next-generation I/O interface that extends the communication fabric from the wafer edges. The interface is modular, programmable, low-latency, and high-bandwidth, using direct wafer link interfaces and a standard RoCE network protocol. Cerebras lists aggregate bandwidth at 2.4 Tb/s with latency around 3 microseconds, while network latency between wafers is said to be 1.7 times higher.
In raw AI compute, CS-4 is a substantial step up from CS-3. The previous CS-3 rack delivered 125 PFLOPs from one WSE-3 chip. CS-4 increases that to 750 PFLOPs using three WSE-3T chips, with each chip contributing 250 PFLOPs. SRAM capacity also rises from 44 GB on CS-3 to 132 GB on CS-4, with 44 GB per WSE-3T chip.
Cerebras says the CS-4 is already in early access, with general availability planned for the third quarter of 2026. The system is being positioned for large-scale AI inference workloads, including frontier models with trillions of parameters.
The company is not stopping with CS-4. Cerebras has also shared early details about its next-generation CS-5 and CS-6 platforms.
CS-5 is expected to arrive in 2027 and is being designed to push AI inference speed and energy efficiency even further. Cerebras says the platform will scale from 30-billion-parameter models to multi-trillion-parameter AI models. For workloads such as Gemma 4 31B and gpt-oss 120B, the company estimates performance of up to 10,000 tokens per second per user. For larger frontier-class models such as DeepSeek, Kimi, and GPT 5.6 SOL, CS-5 is projected to reach up to 5,000 tokens per second per user, with up to 3 million tokens per second per megawatt.
CS-6 is even more ambitious. Cerebras says this future system will take advantage of 3D packaging, a yield-resilient architecture, vertical power delivery, and fully integrated cooling. The next Wafer Scale Engine planned for CS-6 is expected to stack wafer-scale SRAM on top of the compute wafer through 3D integration. The goal is to deliver significantly higher performance in a much smaller footprint while targeting some of the fastest AI inference speeds available.
With CS-4, CS-5, and CS-6, Cerebras is clearly betting that wafer-scale computing will become increasingly important as AI models continue to grow. Instead of scaling by connecting many smaller chips together, Cerebras is expanding around a massive single-wafer architecture with extreme bandwidth, integrated power, advanced cooling, and modular rack-level deployment.
As AI companies search for faster inference, lower latency, and better power efficiency, the Cerebras roadmap shows how aggressively the industry is moving beyond traditional accelerator designs. If the company’s performance and efficiency claims translate into real-world deployments, its wafer-scale AI systems could become a serious force in next-generation AI data centers.
