With the arrival of AMD’s innovative 3D V-Cache CPUs, tech enthusiasts have been curious about why the company didn’t apply the extra cache across all CCDs (Core Chiplet Dies). Recently, AMD provided some clarity on this decision, which turns out to be more about economics than technology.
AMD has introduced its latest Zen 5 3D V-Cache CPUs, namely the Ryzen 9 9950X3D and the Ryzen 9 9900X3D. These processors boast a dual CCD layout, presenting a robust leap in performance thanks to the enhanced Zen 5 architecture. While this setup currently features the 3D V-Cache on just one of the CCDs, many wonder if utilizing it on both could push performance even further.
When questioned about this by HardwareLuxx, AMD revealed that there are no technical barriers preventing the use of 3D V-Cache on both CCDs. The core reason lies in the cost—producing such a processor would simply be too expensive. Moreover, they mentioned that games do not significantly benefit from having a second CCD equipped with a 3D V-Cache compared to the performance gains seen when upgrading from 32 to 96 MB L3 cache on a single CCD.
It turns out that adding a dual 3D V-Cache setup isn’t just cost-prohibitive; it could also lead to inefficiencies in thread scheduling. For optimal performance, threads should ideally remain on the cores with 3D V-Cache. However, if threads were to move dynamically across both CCDs, it wouldn’t harness the full potential of the system, thereby making it less advantageous for AMD.
Interestingly, AMD has experimented with a dual 3D V-Cache configuration during testing stages but decided against bringing it to market. This choice signals that while such CPUs might not appear in the consumer market soon, they could find their place in niches where the trade-off between cost and necessary performance is justifiable.
AMD’s strategic decision balances both innovation and practicality, leaving room for potential advancements in specialized applications in the future.
