AMD is quietly laying the groundwork for a major jump in performance and efficiency with Zen 6—and the first real taste of that shift is already visible in Strix Halo APUs. A recent package analysis points to a new die-to-die interconnect strategy that swaps traditional high-speed serial links for a wide, parallel fan-out approach. The result: lower power, lower latency, and bandwidth that scales more gracefully as on-package demands grow.
Until now, AMD’s chiplet-based CPUs have relied on SERDES PHYs at the edges of the CCDs to shuttle data as serialized bitstreams across an organic substrate to an I/O or SoC die. It’s a proven method that dates back to Zen 2, but it comes with baggage. Serializing and deserializing data isn’t free—you pay in energy for clock recovery, equalization, and coding, and you pay in latency each time data is converted to and from serial form. As long as communication needs were modest, that trade-off was acceptable. With today’s AI-accelerated designs, integrated NPUs, and ever-hungrier CPU fabrics, the overhead is harder to ignore.
Strix Halo changes the equation. Instead of pushing everything through big SERDES blocks, AMD appears to be using TSMC’s InFO-oS packaging with a redistribution layer to route many short, skinny, parallel wires directly between dies. Think of it as placing wide data highways right under the silicon, inside the “interposer-like” fan-out region, rather than relying on a few super-fast, long-distance serial lanes. Physical clues back this up: a rectangular field of tiny pads consistent with a fan-out implementation, plus the conspicuous absence of the large SERDES block traditionally used for die-to-die traffic.
This parallel fan-out architecture offers immediate payoffs:
– Lower latency, because there’s no need to serialize and deserialize data at each hop
– Lower power, thanks to reduced equalization, recovery, and encoding overhead
– Scalable bandwidth, achieved by adding more parallel ports across the CPU fabric instead of cranking serial link speeds
That’s especially important as NPUs and GPUs increasingly sit beside CPU chiplets, all vying for high-throughput, low-latency access to memory and each other. The new interconnect gives AMD a more efficient fabric to tie these parts together, setting the stage for stronger AI, gaming, and content creation performance in future processors.
This approach isn’t without challenges. Multi-layer RDL design is complex, and routing priorities change when the space beneath the dies is populated with dense fan-out wiring. But the potential upside is significant enough that it’s a logical direction for AMD’s next generation.
In short, Strix Halo looks like a preview of what’s coming with Zen 6: a modernized die-to-die interconnect built on TSMC’s InFO-oS and RDL that trades SERDES complexity for wider, leaner parallel links. If this strategy carries forward as expected, Zen 6 could deliver a notable leap in efficiency and responsiveness right where it matters most—inside the package, between the dies that power the entire platform.
