TSMC CoWoS Capacity Could Double by 2028 as AI Chip Demand Keeps Surging
TSMC is reportedly preparing for a major expansion of its advanced chip packaging capacity, driven by relentless demand for AI processors. According to information circulating in Taiwanese media, the company could double its chip-on-wafer-on-substrate, or CoWoS, output by 2028 compared with expected 2026 levels.
CoWoS has become one of the most important packaging technologies in the artificial intelligence hardware market. It is widely used for high-performance AI GPUs because it allows logic chips and high-bandwidth memory to work together with extremely fast communication, low latency, and strong power efficiency. As AI data centers continue to grow, demand for this packaging method has outpaced supply, creating a bottleneck across the semiconductor industry.
The report suggests TSMC’s CoWoS capacity could reach around 260,000 wafers per month by the end of 2028. That would be a significant jump from an estimated 130,000 wafers per month by the end of this year. The expansion is expected to involve TSMC’s AP7 facility in Taiwan as well as its Arizona campus in the United States.
TSMC’s Arizona site is designed to produce advanced chips, but packaging remains a key challenge. At present, much of TSMC’s advanced packaging capability is concentrated in Taiwan, meaning chips manufactured in the U.S. may still need to be transported overseas for packaging. Expanding CoWoS-related capacity outside Taiwan could become increasingly important as customers look for more geographically diverse supply chains.
The AI chip boom has made advanced packaging just as critical as chip manufacturing itself. Modern AI accelerators rely on high-bandwidth memory placed close to the main processor. CoWoS enables this by using an interposer, which acts as a high-speed communication layer between the logic chip and memory. This interposer includes through-silicon vias, or TSVs, which help deliver the bandwidth required for large-scale AI workloads.
Because of these advantages, CoWoS is especially well suited for power-hungry AI GPUs used in training and inference systems. However, the complexity of the technology has made capacity expansion difficult. As a result, the shortage has opened opportunities for other packaging providers and alternative technologies.
One major alternative being watched by the industry is Intel’s EMIB-T technology. Unlike CoWoS, which uses an interposer, EMIB-T relies on small embedded bridge connections placed within the organic substrate. These bridges allow different chip components, such as logic dies and memory, to communicate without requiring a full silicon interposer.
Analysts cited in the Taiwanese report estimate that Intel’s EMIB-T capacity, when converted into an equivalent 12-inch CoWoS wafer measurement, could reach 15,000 to 20,000 wafers per month in 2027. By 2028, that figure could rise to between 40,000 and 45,000 wafers per month.
While EMIB-T differs from CoWoS in design and implementation, it may be attractive for custom AI accelerators. Companies developing their own AI chips, including major cloud computing providers, often have different design needs than GPU makers. This could make alternative packaging methods more appealing in certain applications.
The shortage of CoWoS capacity has also increased demand for other semiconductor packaging firms, including Amkor, UMC, and ASE. These companies may benefit as AI chip designers and foundry customers look for additional capacity to avoid delays.
TSMC’s potential CoWoS expansion highlights how advanced packaging has become a central battleground in the semiconductor industry. In previous chip cycles, much of the focus was on process nodes and transistor density. Today, packaging technologies are playing an equally important role in determining performance, efficiency, and supply availability.
If the reported expansion plans move forward, TSMC could strengthen its position as the leading supplier of advanced packaging for AI chips. At the same time, growing competition from alternative approaches may give chip designers more options as demand for AI hardware continues to climb.
With artificial intelligence driving massive investment in data centers, accelerators, and high-bandwidth memory, the race to expand advanced packaging capacity is likely to remain one of the most important trends in the global semiconductor market through 2028.
