Huawei’s Tau Scaling Claim Draws Skepticism From Semiconductor Analyst
Huawei’s recent announcement around its Tau scaling technology has sparked fresh debate in the semiconductor industry. The company suggested that its approach could help achieve transistor-density benefits comparable to advanced 14 Angstrom-class manufacturing technologies from leading chipmakers such as TSMC and Intel.
However, semiconductor analyst Dr. Ian Cutress has questioned the way Huawei framed the announcement, arguing that the company may be comparing different measures of chip progress. In his view, Huawei’s claim mixes system-level improvements with traditional transistor-density metrics, making the comparison potentially misleading.
Huawei’s position comes at a time when the company faces major restrictions on access to cutting-edge chipmaking tools, especially Extreme Ultraviolet lithography, or EUV. EUV machines are essential for manufacturing the most advanced semiconductor nodes because they allow chipmakers to print extremely tiny circuit patterns, enabling more transistors to fit into a smaller area.
Without access to these tools, Huawei appears to be shifting focus away from conventional Moore’s Law scaling. Moore’s Law has long been used as a benchmark in the chip industry, describing the trend of transistor counts increasing significantly over time while costs improve. Cutress believes Huawei is now trying to broaden the definition of chip advancement by emphasizing full-system optimization rather than transistor density alone.
According to Cutress, the idea behind Tau scaling is not necessarily wrong. Improving overall performance through better packaging, chip stacking, interconnects, memory integration, and system design can deliver real gains. The issue, he argues, is that Huawei is presenting this as if it redefines the industry’s core scaling roadmap, when similar ideas have been studied and developed by major semiconductor companies for many years.
A key part of the discussion involves hybrid bonding and 3D chip stacking. Hybrid bonding is an advanced packaging technique that connects chip layers more directly and densely than older methods that rely on microbumps. This allows different chip components to be stacked or connected with shorter, faster, and more efficient pathways.
Cutress pointed out that companies such as AMD, Intel, and TSMC have been researching and commercializing related technologies for years. Intel’s embedded multi-die interconnect work, for example, dates back well over a decade, while chip-on-chip stacking has gradually moved from research into real products.
The technical challenge is the pitch, or the distance between the centers of two interconnect points. Smaller pitch sizes allow more connections between stacked chips, improving bandwidth and efficiency. Early hybrid bonding implementations had pitches around 9 microns, while leading roadmaps have moved toward smaller values, including around 4 microns. Research has explored even more aggressive scaling, but moving from a lab demonstration to mass production is extremely difficult.
Huawei’s paper reportedly discusses logic-on-logic stacking with a pitch around 2 microns. If achieved at scale, that would be a significant technical accomplishment. Logic-on-logic stacking means placing computing logic, such as CPU or GPU-related circuitry, on top of other logic layers. This is more complex than stacking memory on logic or logic on memory because heat, power delivery, alignment, yield, and signal integrity become major obstacles.
Cutress emphasized that Huawei’s most notable claim is not simply Tau scaling as a broad concept, but the suggestion that it can use sub-2-micron hybrid bonding for logic-on-logic integration. That would be an impressive breakthrough if it can be manufactured reliably and economically in high volume.
The debate becomes more complicated when Huawei compares this approach with traditional transistor density. In semiconductor manufacturing, density usually means transistors per unit area on a chip. That metric has been used for decades because most chips have traditionally been built as flat, monolithic pieces of silicon.
Stacking chips changes the discussion. If a company places one logic layer on top of another, it may increase the number of transistors within the same footprint. From a system or packaging perspective, that looks like higher density. But from the standpoint of silicon manufacturing, each layer still has its own transistor density, and the total amount of silicon used has not magically become equivalent to a more advanced lithography node.
Cutress compared the situation to building a second floor on a house. In urban planning terms, the number of rooms per plot of land increases. But in construction terms, the size and structure of each floor remain separate considerations. His point is that Huawei appears to be using a packaging-style density argument, while the broader chip industry typically uses a manufacturing-area-based density metric.
This is why he described the comparison as an “apples and oranges” situation. Huawei may be making progress in advanced packaging and 3D integration, but that does not necessarily mean it has matched the transistor density of cutting-edge 14A-class process technology in the conventional sense.
Another major challenge is manufacturing efficiency. Hybrid bonding can require significant energy and extremely precise production conditions. Cutress noted that the energy needed for hybrid bonding per square centimeter can be much higher than what is required for leading-edge EUV transistor manufacturing. More energy and complexity can slow production and make it harder to achieve strong yields, which is critical for commercial success.
In other words, demonstrating a technology once is very different from producing millions of chips with consistent quality. Semiconductor breakthroughs only become industry-changing when they can be manufactured at scale, with acceptable cost, performance, power efficiency, and yield.
Cutress also commented on Huawei’s research paper, saying parts of the writing appeared unusual and may have involved AI assistance or AI-based translation. He pointed to short, repetitive sentence structures and word choices that he felt resembled machine-generated text. However, he also acknowledged that translation could be a factor, especially when technical material is being converted between languages.
The broader takeaway is that Huawei’s Tau scaling strategy reflects the company’s need to find alternative paths forward in semiconductor development. Since access to the most advanced lithography equipment is restricted, Huawei appears to be accelerating investment in packaging, stacking, and system-level design.
That strategy could still be meaningful. Advanced packaging is becoming one of the most important areas in the chip industry, especially as traditional transistor scaling becomes more expensive and difficult. Companies are increasingly using chiplets, 3D stacking, hybrid bonding, and specialized interconnect technologies to improve performance without relying only on smaller process nodes.
But according to Cutress, Huawei’s announcement should be viewed carefully. Tau scaling may be a useful framework for describing broader system optimization, yet it does not erase the difference between improving a chip system through stacking and achieving the same transistor density as a cutting-edge manufacturing node.
Huawei’s biggest potential achievement here is its reported progress in fine-pitch hybrid bonding and logic-on-logic stacking. If the company can turn that into reliable mass production, it could strengthen its position in advanced semiconductor packaging. But claiming equivalence with the most advanced transistor-scaling technologies may be an overreach unless the metrics are clearly defined.
For now, the semiconductor industry will likely watch Huawei’s Tau scaling efforts closely. The concept highlights an important shift in chip design: future performance gains may come not only from smaller transistors, but also from smarter ways of connecting, stacking, and optimizing entire computing systems.
