As the arena of high-performance computing (HPC) and artificial intelligence (AI) continuously evolves, the industry leader Synopsys has made a breakthrough by announcing the release of the first complete PCIe 7.0 IP solution. This groundbreaking technology is designed to propel the capabilities of the next generation of supercomputing chip designs. With an impressive data transfer rate of up to 512 GB/s, this IP solution is poised to transform the computational landscape.
Driving AI and HPC to New Heights with Synopsys’ PCIe 7.0 IP Solutions
The demands for faster, more robust computational power are surging, particularly as complex and large language models become more prevalent. These models, often comprising trillions of parameters, require swift and reliable processing capabilities. Addressing this critical need, Synopsys has developed the industry’s only PCIe standards-based solution that ensures secure and high-speed data transfers at unparalleled rates.
In June 2024, Synopsys is set to unveil and demonstrate its pioneering technology at the PCI-SIG Developers Conference to be held in Santa Clara. This event will highlight the capabilities of PCIe 7.0 IP technology and how it serves the increasingly data-intensive workloads of AI and supercomputing tasks.
Unlocking the Full Potential of PCIe 7.0 IP
Synergizing controller, PHY, IDE security module, and verification IP, Synopsys’ PCIe 7.0 IP solution is tailored to minimize the integration risks associated with AI and HPC networking chips. The integration of the PCIe 7.0 Controller IP facilitates low latency, ensuring efficient data transmission across the network. Further enhancing interoperability, these solutions support backward compatibility through a comprehensive root complex to endpoint connection.
The PCIe 7.0 PHY IP stands out with its exceptional signal integrity at staggering speeds of up to 128 Gb/s per lane. Its compatibility with CXL Controller IP solutions promises seamless integration without compromise. To bolster security, the Synopsys Integrity and Data Encryption (IDE) Security IP defends against hardware-level attacks by ensuring data confidentiality and integrity.
For designers and engineers looking to verify and validate their designs with greater speed, Synopsys also provides PCIe 7.0 Verification IP and hardware-assisted verification solutions. These come equipped with built-in protocol checks and various controller and PHY configurations, all aimed at accelerating the move towards silicon success.
Synopsys’ Comprehensive IP Portfolio for HPC
Synopsys has established itself with the broadest high-speed interface IP portfolio for HPC system-on-chip (SoC) designs. This spans secure IP solutions, 1.6T/800G Ethernet, CXL, and HBM. Synopsys’ commitment to comprehensive interoperability testing, robust IP performance, and dedicated technical support enables designers to surmount the challenges of advancing to silicon production swiftly and efficiently.
Anticipation for the Future with PCIe 7.0 IP
The anticipation surrounding the commercial availability of the Synopsys PCIe 7.0 Controller with IDE Security and PHY IP for advanced processes is intense. Set for an early 2025 release, this technology is on the cusp of launching a new epoch in supercomputing.
In an era defined by rapid technological advancements and soaring data demands, Synopsys’ unveiling of PCIe 7.0 IP solutions symbolizes a critical step forward in meeting the future head-on. As it becomes available, it will surely be a cornerstone for the next-wave innovations in AI and HPC, fostering the development of computational capabilities previously unattained.
