Qualcomm is preparing a major push into the AI data center market with a new memory-focused technology called HBC, short for High-Bandwidth Compute. The company says the design is built to tackle one of the biggest challenges facing modern AI systems: the memory wall.
As artificial intelligence models become larger and more demanding, accelerators need more than raw compute power. They also need fast, efficient access to massive amounts of memory. Without enough memory bandwidth and capacity, even powerful AI chips can be held back. Qualcomm’s HBC approach is designed to reduce that bottleneck by bringing compute closer to memory in a highly integrated 3D chip design.
During its Investors Day 2026 presentation, Qualcomm described HBC as a purpose-built near-memory accelerator that combines compute with significantly improved memory bandwidth. Instead of relying only on traditional memory layouts, the company is using a stacked architecture that places the HBC accelerator underneath an LPDDR memory stack.
LPDDR was chosen because it can offer large memory capacities while maintaining strong power efficiency. The memory stack is connected to the HBC accelerator using TSVs, or through-silicon vias, which allow dense vertical connections between chip layers. This 3D integration is intended to deliver much higher bandwidth while keeping energy usage under control.
Qualcomm is positioning HBC as an alternative path to the current AI memory trend, where HBM is widely used in high-performance accelerators. While HBM offers strong bandwidth, Qualcomm argues that rising power demands and increasing token-processing costs are pushing up total cost of ownership for AI infrastructure. HBC is designed to lower energy consumption per token, improve memory bandwidth, and reduce overall operating costs for data center customers.
The company says the architecture is based on four key strengths: advanced 3D integration, system-level design, leadership in LPDDR memory technology, and long-standing expertise in power-efficient computing. These areas are central to Qualcomm’s strategy as it attempts to compete in the rapidly expanding AI data center hardware market.
The first version, known as HBC Gen1, will debut with Qualcomm’s upcoming AI250 accelerator. In this design, the HBC-enhanced LPDDR memory stack will sit on the same 2D organic substrate as the AI250 chip. Qualcomm claims each AI250 accelerator card will deliver up to 133 TB/s of memory bandwidth, which would represent an 18x increase compared with the AI200 platform using LPDDR5X.
The performance-per-watt claims are also ambitious. Qualcomm says HBC can deliver up to 6x more bandwidth per watt compared with HBM and up to 200x more capacity per watt compared with SRAM. If these figures hold up in real-world AI workloads, HBC could give data center operators a compelling new option for scaling AI inference and training more efficiently.
Memory capacity and bandwidth have become critical issues across the AI industry. Larger models, longer context windows, and higher token throughput all place enormous pressure on memory systems. Qualcomm’s HBC technology is aimed directly at this problem, with the goal of making AI accelerators faster, more power-efficient, and less expensive to run at scale.
The first HBC Gen1 products paired with the AI250 accelerator are expected to arrive around mid-2027. Qualcomm is already planning a second-generation version, HBC Gen2, for 2028. That next step is expected to launch alongside the AI300 accelerator and deliver up to a 54x improvement in effective bandwidth compared with AI200, along with a 7x increase in bandwidth per watt compared with HBM.
With HBC, Qualcomm is signaling that the future of AI acceleration may depend as much on memory innovation as on compute performance. By stacking compute closer to high-capacity LPDDR memory, the company hopes to address the memory bottlenecks limiting next-generation AI systems and reduce the cost of running large-scale AI workloads in data centers.
