Intel’s next wave of mobile silicon is coming into focus, and the latest close-up die shot offers the best look yet at the Panther Lake compute tile built on the 18A process. This generation, branded as Core Ultra Series 3, blends fresh CPU microarchitectures with upgraded graphics, NPU blocks, and a revamped media engine, all wrapped in advanced Foveros packaging.
At the heart of the reveal is the 18A compute tile, which integrates next-gen Cougar Cove performance cores, Darkmont efficiency cores, and Darkmont LP-E cores, alongside L2 and L3 cache structures. The image, shared by Game.Keeps.Loading with analysis from Chips and Cheese, shows three Darkmont clusters, each containing four E-cores, plus two Cougar Cove P-cores installed with two additional P-core sites left empty—suggesting this sample isn’t fully populated.
Panther Lake is built from multiple tiles and layers, each on the process node best suited to the job:
– Compute Tile: Intel 18A
– Graphics Tile: Intel 3 or TSMC N3E
– Platform Controller Tile: TSMC N6
– Base Tile: Intel 1227.1
– Filler Tile: N/A
– Foveros package
– CPU interposer package
Early die measurements point to notable density gains on the efficiency side and a tightly optimized performance core:
– Cougar Cove P-Core: approximately 4.49 mm²
– Darkmont E-Core (per core): approximately 0.95 mm²
– Darkmont E-Core cluster: approximately 6.47 mm²
Compared with recent generations, Cougar Cove lands roughly in line with Lion Cove (about 4.45 mm²) and smaller than Redwood Cove (about 5.33 mm²). On the efficiency front, Darkmont is about 13% smaller per core than Skymont (about 1.09 mm²) and also trims roughly 5% off the cluster area versus Skymont clusters (about 6.79 mm²). Crestmont sits between them for per-core area (about 1.04 mm²), with clusters around 5.90 mm². These reductions hint at higher core density and potentially better efficiency for multi-threaded and background workloads.
Cache topology is also evolving. Based on the current readout, the configuration appears as follows:
– Cougar Cove P-Core (per core): 3 MB L2 + 256 KB L1
– Cougar Cove P-Core sub-cache: 192 KB L1D + 48 KB L0D
– Darkmont E-Core (per cluster): 4 MB L2 + 96 KB L1
– Darkmont E-Core sub-cache: 64 KB L1I + 32 KB L0D
The combination of an 18A compute tile, updated core layouts, and a modular multi-tile design positions Panther Lake to deliver a meaningful leap in performance-per-watt, responsiveness, and graphics/NPU capabilities in thin-and-light systems. While these details stem from a pre-launch glimpse, they line up with Intel’s stated goals for the architecture and packaging strategy.
After hands-on sessions during Tech Tour 2025, all signs point toward a full unveil at CES 2026. Expect more concrete specifications, finalized core counts across SKUs, and deeper dives into the graphics, NPU, and media engines as launch approaches.
