Marvell Structera CXL aims to boost AI memory capacity with real-time compression
As artificial intelligence systems grow larger and more demanding, memory has become one of the biggest bottlenecks in modern data centers. AI workloads require enormous memory capacity and high bandwidth, while the broader technology industry continues to deal with pressure on memory supply, rising costs, and increasing demand for efficient infrastructure.
Marvell is addressing this challenge with its Structera CXL controller family, a new class of Compute Express Link memory solutions designed to make better use of available DRAM. The key feature is inline data compression, allowing systems to store more information in memory without relying on the host CPU to handle compression tasks.
The company has introduced two main products in this lineup: Structera X and Structera A. Both are built around Marvell’s CXL controller technology and include a dedicated Compression-Decompression Block, known as CDB. This hardware block compresses data as it is written to DRAM and decompresses it as it is read, all in real time.
That matters because traditional software-based compression can consume valuable CPU resources and introduce additional overhead. Marvell’s approach moves this work into dedicated silicon, helping preserve host processor performance while improving effective memory capacity and bandwidth utilization.
The Compression-Decompression Block uses a custom version of the LZ4 lossless compression algorithm. LZ4 is known for its balance of speed, low latency, and solid compression ratios, making it well suited for memory-intensive workloads where performance is critical. According to Marvell’s data, Structera hardware can achieve compression performance close to host-side LZ4 while removing the need for software-driven compression.
Structera X is designed as a CXL memory expansion controller. It supports both DDR5 and DDR4 memory, making it flexible for different server platforms and infrastructure upgrades. The controller includes four Arm Cortex-M7 cores, the dedicated CDB compression engine, multi-channel DMA, 56 MB of last-level cache, four DDR channels, and inline AES-XTS 256-bit memory encryption and decryption.
Structera X supports CXL 2.0 and PCIe 5.0 with either a single x16 port or dual x8 ports. It delivers up to 200 GB/s of memory bandwidth and supports up to three DIMMs per channel. In terms of capacity, it can handle more than 6 TB of DDR5 DRAM or more than 4 TB of DDR4 DRAM. It also includes secure boot and an embedded hardware security module, making it suitable for enterprise and data center deployments where memory security is a priority.
Structera A takes a different approach. Rather than focusing only on memory expansion, it is positioned as a near-memory accelerator designed to improve memory access performance. It includes 16 Arm Neoverse V2 cores running at 3.2 GHz, four Arm Cortex-M7 cores, the same CDB compression engine, 64 MB of last-level cache, and four DDR5 memory channels.
Structera A supports CXL 2.0 and PCIe 5.0 through an x16-port controller and offers up to 200 GB/s of memory bandwidth. It supports four DDR5-6400 memory channels with up to two DIMMs per channel. Like Structera X, it includes inline LZ4 compression and decompression, inline XTS-AES 256-bit encryption and decryption, secure boot, and a hardware security module.
The performance numbers show why this technology could be important for AI servers and cloud infrastructure. Marvell says the CDB supports 4 KB and 1 KB page sizes, configurable compression effort levels from 0 to 3, and a maximum compression ratio of 64:1 for all-zero pages.
For real-world data types, Structera’s compression results vary depending on the workload. XML data reaches around 2.75x compression, database data can reach about 3.64x, source code achieves roughly 2.00x, web content reaches around 1.67x, natural language data delivers about 1.32x, and binary or compiled data reaches around 1.68x. These results are similar to host-side LZ4 compression, but with the advantage of being handled directly by the memory controller hardware.
This could have major implications for AI infrastructure. Large language models, recommendation engines, high-performance computing workloads, and cloud databases all depend heavily on memory capacity and bandwidth. By improving effective DRAM usage, inline CXL compression may help data centers delay costly memory upgrades, improve server efficiency, and increase workload density.
The timing is also important. As AI adoption accelerates, demand for high-capacity memory continues to rise. Technologies that can stretch existing memory resources without sacrificing performance are becoming increasingly valuable. Marvell’s Structera CXL controllers are designed to meet that need by combining CXL memory expansion, hardware-level compression, encryption, and security features into a single platform.
With Structera X focused on memory expansion and Structera A built for near-memory acceleration, Marvell is positioning its CXL portfolio as a practical solution for the next generation of AI and data center workloads. If memory supply remains tight and AI models continue to grow, hardware-based compression could become a key feature in future server designs.
