Intel’s next wave of Xeon processors, codenamed Diamond Rapids, is moving closer to reality, and early platform details are starting to surface. Shipping logs referencing Intel’s Johnson City reference platform point to powerful, power-hungry parts designed for next-generation data center performance.
The Johnson City platform, identified as JNC in the listings, appears to be Intel’s in-house and partner validation hardware for Diamond Rapids. Entries labeled as “Validation Material” mention a “JNC Server Board” and include part codes that hint at aggressive power targets. One listing suggests a 500W class CPU (“1SPC 500 DMR”), while another references a 650W TDP configuration. There’s also a “JNC Multi-S” platform tagged “2+1+1S,” which likely denotes a multi-socket or multi-chiplet setup alongside a single-socket variant, reflecting a flexible validation environment for different Diamond Rapids configurations.
Diamond Rapids is expected to leverage Intel’s 18A process and use Panther Cove performance cores, with core counts rumored to reach as high as 192—and potentially up to 256 in some configurations. While Intel has not confirmed final specs, the platform direction clearly targets extreme compute density, memory bandwidth, and IO scalability.
A major architectural shift appears to be in memory topology. Reports indicate the Diamond Rapids “Xeon 7” range will be limited to 16-channel configurations, signaling a move away from mainstream 8-channel platforms in this generation. With core counts scaling up, a wider memory interface can help keep per-core bandwidth competitive, especially for AI inference, cloud-native workloads, and memory-intensive databases.
Socket infrastructure is getting a dramatic upgrade too. Diamond Rapids is slated to use the enormous LGA 9324 socket—significantly larger than client platforms like LGA 1700 and even bigger than the already massive LGA 7529 expected for Granite Rapids. The shift underscores higher pin counts for more memory channels, expanded IO, and tighter power delivery to support 500W–650W processors.
On the IO front, expectations include next-gen connectivity and a pathway to PCIe 6.0, depending on final platform timing. Earlier roadmaps place Diamond Rapids within Intel’s high-core-count lineup alongside Granite Rapids and Sierra Forest, with follow-up Coral Rapids slated to reintroduce SMT according to prior disclosures.
While Intel has yet to announce a release date, the current outlook points to a 2026 launch window, likely in the second half of the year. When it arrives, Diamond Rapids will square off against AMD’s next-generation EPYC family known as Venice, setting the stage for a fierce battle in performance, power efficiency, and total platform capability.
Key takeaways
– Johnson City (JNC) is the reference platform for Diamond Rapids validation.
– Early logs point to 500W and 650W TDP tiers, signaling extremely high-performance SKUs.
– Diamond Rapids is expected to use Intel 18A, Panther Cove cores, and a massive LGA 9324 socket.
– “Xeon 7” parts are reportedly 16-channel only, emphasizing memory bandwidth for high core counts.
– Launch is expected around 2026, with direct competition against AMD’s EPYC Venice lineup.
What this means for data centers
– Planning for higher TDPs and larger sockets will be crucial; advanced cooling and power delivery will likely be mandatory in many deployments.
– The move to wider memory channels targets better scalability for AI, analytics, and cloud workloads.
– If PCIe 6.0 and expanded lane counts are realized at scale, accelerators and high-speed storage networks will benefit from improved throughput.
As always with pre-launch platforms, specifications can change, but the direction is clear: Diamond Rapids aims to push Xeon into ultra-high-core, high-bandwidth territory, setting a new bar for x86 servers in the second half of the decade.
