Intel is pushing deeper into custom chips as Lip-Bu Tan reshapes the company
Intel is moving through one of the most important reinventions in its recent history. Under CEO Lip-Bu Tan, the chipmaker is working to cut through layers of internal bureaucracy, speed up decision-making, and pursue fast-growing markets where its manufacturing and design expertise can become more valuable.
One of the biggest opportunities now in focus is the ASIC market. ASICs, or application-specific integrated circuits, are custom chips built for specific workloads. In today’s technology landscape, that increasingly means AI acceleration, cloud computing, networking, security, and data center infrastructure. As demand for specialized silicon continues to surge, Intel appears determined to win a larger share of this rapidly expanding business.
A key sign of that shift is Intel’s hiring of Dean Jarnac, a former Marvell executive with deep experience in custom chip design. Tech analyst Jack Gold has suggested that Jarnac’s background could help Intel better understand how to compete for ASIC contracts, particularly with customers looking for highly specialized processors rather than traditional off-the-shelf chips.
This move also reflects a broader leadership change under Lip-Bu Tan. Intel has long been known for promoting from within, but Tan has been bringing in outside executives to lead major business areas. That signals a clear attempt to break old habits and bring fresh thinking into parts of the company that need to move faster.
The ASIC market has become one of the hottest areas in semiconductors. Major technology companies are increasingly designing custom chips to reduce dependence on general-purpose processors and improve performance for specific tasks. Google has its Tensor Processing Units, Amazon has Trainium chips, Microsoft is developing Maia AI accelerators, and other AI-focused companies are also moving toward custom silicon.
That trend creates a massive opening for companies that can design, manufacture, package, and scale advanced chips. Intel wants to be one of those companies.
Jarnac’s experience could be especially valuable because custom chip development requires a different mindset from Intel’s traditional business. Intel has historically designed and manufactured many of its own processors. ASIC customers, however, often need a partner that can understand their workload, design around specific performance targets, and support complex manufacturing requirements.
As Jack Gold noted, someone with experience at a chip design-focused company understands how the custom silicon process works from the customer’s point of view. That may help Intel become more competitive as it tries to win deals in AI, networking, security, and cloud infrastructure.
Intel has already shown signs of progress. In July, the company announced an agreement to design and manufacture Fortinet’s next-generation security processor. That chip is expected to power high-performance firewalls and advanced security infrastructure, giving Intel a foothold in a specialized market where performance, efficiency, and reliability are critical.
The company’s financial targets suggest this is more than a side project. Intel CFO David Zinsner said in July that the ASIC business was approaching a $2 billion annual run rate. He also indicated that it could grow to $4 billion in the not-too-distant future. For a company looking to strengthen its foundry and custom silicon operations, that kind of growth could become an important pillar of its turnaround strategy.
Intel’s ASIC push also fits closely with its broader manufacturing ambitions. The company has been investing heavily in advanced process nodes and packaging technologies, both of which are essential for next-generation chips. In markets such as AI acceleration and high-performance computing, chip performance is no longer determined only by transistor density. Packaging, memory bandwidth, power delivery, and interconnect performance are now just as important.
That is where Intel’s Foveros technology could become a major advantage. Foveros enables true 3D chip stacking, allowing active dies to be placed directly on top of other dies or interposers. This approach can improve performance by shortening the distance that signals need to travel, reducing latency, and increasing interconnect density.
In simple terms, Foveros allows Intel to build more advanced chip packages by stacking components vertically instead of placing everything side by side. This is especially useful for AI chips, data center processors, and custom accelerators that need massive bandwidth and low power consumption.
Foveros represents a step beyond Intel’s EMIB technology. EMIB, or Embedded Multi-die Interconnect Bridge, connects multiple chiplets inside a single processor package using tiny silicon bridges placed within the package substrate. This allows different parts of a chip to communicate with high bandwidth without requiring a large, expensive silicon interposer.
Intel has also developed EMIB-T, which adds Through-Silicon Vias, or TSVs, to the embedded bridge structure. These vertical pathways allow power and signals to move more directly through the package, supporting more advanced forms of 3D integration.
Together, technologies like EMIB, EMIB-T, and Foveros give Intel a stronger position in the chiplet era. As chips become more complex, companies are increasingly combining different types of silicon into one package. A future AI accelerator, for example, might combine compute tiles, memory, networking components, and specialized logic in a tightly integrated design. Advanced packaging makes that possible.
Intel is also quietly working on new memory-related technologies that could support its long-term strategy. Among them are XBM and Z-Angle Memory, also known as ZAM. ZAM is a 3D-stacked DRAM concept that replaces traditional vertical TSVs with diagonal interconnects. This design can create a central thermal pathway that helps move heat away more efficiently.
Better thermal management is crucial for stacked memory because heat becomes a major challenge when components are layered vertically. ZAM also uses copper-to-copper hybrid bonding and avoids capacitors, potentially allowing for higher density and improved efficiency.
Intel’s interest in advanced memory is not accidental. AI and high-performance computing workloads are often limited by memory bandwidth rather than raw compute power. If Intel can pair custom ASICs with advanced packaging and next-generation memory technologies, it could offer customers a more complete platform for demanding workloads.
The company has also highlighted its hiring of Shou-Chi Lee, the former CEO of SK hynix, while discussing memory-related ambitions. That move further supports the idea that Intel is bringing in outside expertise to strengthen areas that will matter in the next phase of semiconductor competition.
Lip-Bu Tan’s strategy appears clear: make Intel faster, more flexible, and more attractive to major customers looking for custom silicon solutions. Hiring leaders with deep industry experience, targeting high-growth ASIC opportunities, expanding advanced packaging capabilities, and exploring future memory technologies all point in the same direction.
The challenge, of course, is execution. The custom chip market is competitive, and many major cloud and AI companies already work with experienced semiconductor partners. Intel must prove that it can deliver on time, at scale, and with the performance required for next-generation workloads.
Still, the opportunity is significant. If Intel can successfully combine its manufacturing capabilities, packaging technologies, and newly strengthened ASIC leadership, it could become a much more important player in custom AI chips and specialized data center silicon.
For Intel, the ASIC market may not just be another revenue stream. It could become a central part of the company’s broader comeback plan.
