Intel Pushes Advanced Packaging Toward Hyper-Large Chips at Its New Mexico Facility
Intel is moving closer to building some of the largest and most advanced chip packages ever made, thanks to major progress in advanced semiconductor packaging at its Rio Rancho facility in New Mexico. The breakthrough could help enable a new generation of hyper-large chips that scale far beyond today’s traditional reticle limits and deliver the kind of compute performance needed for artificial intelligence, high-performance computing, and future data center workloads.
For decades, chip performance was mostly driven by shrinking transistors and building larger monolithic dies. That approach is becoming increasingly difficult and expensive. Today, the industry is shifting toward chiplet-based designs, where multiple smaller silicon dies are connected inside one package to behave like a single powerful processor.
Intel describes this new era as a kind of silicon mosaic. Instead of relying on one giant piece of silicon, companies can combine specialized tiles for compute, memory, input/output, and acceleration into one tightly integrated package. This approach improves flexibility, performance, scalability, and manufacturing efficiency.
At Intel’s Rio Rancho site, this shift is becoming especially important. The facility, once known for 6-inch wafer manufacturing in the 1980s, has now become a major U.S. hub for advanced chip packaging. Intel is using the site to develop and scale technologies that could expand chip package sizes to 8 times the standard reticle size today and more than 12 times by 2028.
Why advanced packaging matters for future chips
Modern processors are no longer limited to a single die. Technologies such as EMIB and Foveros allow Intel to connect multiple chiplets in advanced ways, enabling faster communication, higher bandwidth, improved power delivery, and denser integration.
EMIB, or Embedded Multi-die Interconnect Bridge, connects chiplets side by side with high-speed links. Foveros enables 3D stacking, allowing silicon dies to be placed vertically. Together, these technologies help Intel create larger and more complex processors without depending entirely on one massive die.
However, as chip packages grow, new engineering challenges appear. It is not enough to simply place more chiplets together. The package must move data quickly, deliver power efficiently, control heat, maintain structural stability, and remain reliable enough for mass production.
Intel is now working on what it calls hyper-large form factor packages. These packages could eventually reach 240mm by 240mm, equal to around 24 times reticle size. That would be far larger than conventional chip packages and could open the door to extremely powerful processors for AI and high-performance computing.
The biggest challenges of building hyper-large chips
As chip packages become larger, every part of the design becomes more difficult. Intel’s research highlights several major hurdles that must be solved before hyper-large chips can become practical.
One major challenge is data movement. AI processors need extremely fast communication between compute tiles, memory stacks, and other chiplets. Intel is using advanced EMIB-T bridges with metal layers finer than 2 micrometers to support speeds of 64 Gb/s per channel inside the package. For connections that leave the package, the company is studying co-packaged copper cable connectors and co-packaged optics as possible ways to reach future off-package speeds of 448 Gb/s.
Power delivery is another critical issue. In very large packages, routing power from the edges becomes inefficient. Intel is exploring embedded silicon capacitors inside the substrate and directly under the chips. These capacitors could provide up to 1 millifarad of local energy storage per full reticle chip area. Moving voltage regulators onto or into the package could also help the system react faster to sudden power changes.
Manufacturing yield is also a major concern. The larger and more complex a package becomes, the greater the chance that one connection or communication lane could fail. Intel proposes adding spare communication lanes alongside active ones. With just three or four spare lanes for every group of 64, bundle yield could rise from around 97% to more than 99%. At hyper-large scale, that difference could determine whether a product is economically viable.
Physical stability is another obstacle. Large packages can warp, which may disrupt electrical connections and reduce contact with cooling hardware. Intel’s research modeled warpage of up to 7mm at room temperature. To address this, the company is combining thick stiffener rings, low-expansion glass-core substrates, and multi-ball solder processes. During operation, cooling hardware may apply more than 4,500 newtons of force to help keep the package nearly flat.
Thermal management may be the toughest challenge of all. Hyper-large packages could operate at 15 to 25 kilowatts, with localized hot spots that require highly advanced cooling. Instead of using one large cold plate, Intel is proposing a modular, cell-based cooling system with independent thermal zones and embedded sensors. This design could scale beyond 5 kilowatts of cooling per module.
Intel solves a key encapsulation problem
One of the most important breakthroughs involves encapsulation. Encapsulation is the process of sealing and protecting the chip package. A material called underfill flows between the chips and the substrate, protecting solder joints and improving reliability.
As packages grow larger, underfill must travel farther. That creates more resistance and increases the risk of air pockets, voids, and defects. In current designs, underfill can typically flow about 43mm with EMIB and around 22mm in standard packages. For chip packages that scale to 5 times, 7 times, or even 10 times reticle size, those distances become much harder to manage.
Intel says it has addressed this challenge using three coordinated improvements: better material, smarter dispensing, and optimized curing.
First, the company developed improved underfill materials that balance long-distance flow with mechanical reliability. Lower viscosity helps the material travel farther, but it must still remain strong enough to protect the package over time. Intel created direct flow tests on representative package designs to identify formulas that could extend flow without weakening the final structure.
Second, Intel changed how the material is applied. Instead of relying mainly on edge dispensing, the company uses a multi-point dispensing strategy. This reduces the distance the underfill must travel and improves coverage across the package.
Third, Intel optimized the curing process. Curing locks the material into place, but it can also create defects if not controlled properly. Intel tuned the cure conditions to collapse voids and produce void-free package designs.
This is a major step toward making hyper-large advanced packages realistic for future production.
Validated chip packages show strong progress
Intel has already validated multiple packages that align with its hyper-large form factor roadmap. One EMIB-based package exceeded 5 times reticle size and included 18 dies, with 12 HBM memory sites. It achieved void-free encapsulation at flow distances of up to 40mm.
The company also validated a larger tiled EMIB package beyond 7 times reticle size, again with void-free results. Using Foveros 3D packaging, Intel achieved void-free encapsulation at 2 times and 4 times reticle scale, with the 2 times design passing full reliability testing.
These results suggest that hyper-large chip packages are no longer just a research concept. They are moving closer to practical manufacturing.
Rio Rancho becomes a key site for advanced chip packaging
Intel’s Rio Rancho facility is playing a central role in this effort. The New Mexico site is becoming one of the most important locations in the United States for advanced semiconductor packaging, especially as demand grows for AI chips, high-bandwidth memory integration, and next-generation data center processors.
Glass substrates may also become a key part of Intel’s long-term roadmap. These substrates can provide better dimensional stability, improved signal integrity, and support for larger package sizes. As the industry moves beyond traditional organic substrates, glass could help enable hyper-large chip designs with better performance and efficiency.
Intel’s roadmap points to continued scaling beyond 7 times reticle size, then beyond 12 times reticle in the near term. Looking further ahead, panel-level packaging could push future designs beyond 50 times reticle size.
What this means for the future of computing
The race to build larger and more advanced chip packages is being driven by the explosive growth of AI, cloud computing, scientific simulation, and high-performance data processing. These workloads need more compute power, more memory bandwidth, and faster chip-to-chip communication than traditional processor designs can easily provide.
Intel’s advanced packaging work could help solve these limitations by allowing many specialized dies to work together inside one enormous package. Instead of building one giant chip, manufacturers can assemble a powerful system of chiplets that behaves like a single compute engine.
If Intel can bring hyper-large packaging into high-volume manufacturing, it could lead to a new class of processors with unprecedented performance density and efficiency. The company’s progress in encapsulation, interconnects, power delivery, thermal management, and glass substrates shows that the future of computing may depend as much on packaging innovation as on transistor scaling.
Intel’s work in New Mexico marks a significant step toward that future, where the world’s most powerful chips are not simply made from smaller transistors, but from smarter, larger, and more advanced chip packages.
