Chinese semiconductor company Innosilicon says it has officially delivered its LPDDR6/LPDDR5X memory controller IP to its first domestic customers, marking an early commercial milestone for China’s push into next-generation mobile memory technology.
The company originally revealed its LPDDR6/LPDDR5X PHY and controller IP last year, positioning it as a platform intended for upcoming high-speed, low-power devices. Now, Innosilicon claims it has secured its first wave of domestic commercial cooperation, bringing the technology closer to real products.
Innosilicon’s LPDDR6/LPDDR5X solution combines a PHY and controller designed on an advanced FinFET process, with a focus on reducing power consumption while increasing bandwidth and keeping latency low. The company also points to its broader experience across modern DRAM-related IP—including GDDR6, GDDR6X, GDDR7, and high-bandwidth memory technologies like HBM3E and HBM4—as groundwork that helped it build a more mature, mass-market-ready LPDDR offering.
One of the headline improvements is speed. Innosilicon lists LPDDR6 I/O performance reaching up to 14.4Gbps. That’s a major jump compared to the company’s earlier LPDDR5X solution, which topped out at 9.6Gbps. To get there, Innosilicon says it used a custom I/O architecture along with process optimizations and SIPI simulation work, resulting in roughly a 1.5x increase in I/O rate.
The bandwidth gains aren’t just about faster signaling. LPDDR6 also shifts the architecture from 16-bit to 24-bit, and expands I/O bit size from 8-bit to 12-bit. In practical terms, this allows a single-channel 24-bit design and delivers up to a 2x bandwidth increase—an upgrade that can directly benefit workloads that thrive on memory throughput, such as on-device AI, advanced mobile gaming, computational photography, and high-resolution video processing.
Innosilicon also highlights a long list of platform features aimed at performance, reliability, and power efficiency.
Key LPDDR6-focused capabilities include support for I/O speeds up to 14.4Gbps, error-correction features such as ECS (auto/manual) and Link ECC, System Meta Function Mode, flexible refresh options including dual/per/all bank refresh (single or burst), read-modify-write with mask write support, dynamic write NT-ODT, DVFSL mode, x24/x48 burst modes, and both normal and dynamic/static efficiency modes.
Common features across the LPDDR6/LPDDR5X controller IP include expandable data width options (x12 to x48 for LPDDR6 and x16 to x32 for LPDDR5X), a built-in performance monitor, transmit pre-emphasis and receive DFE for better signal integrity, LPDDR5X WCK mode and Link ECC support, compatibility with PoP and discrete memory packages, single-rank and multi-rank configurations, PVT compensation plus timing calibration for reliability across operating corners, at-speed BIST and scan insertion with PAD and internal loopback support, multiple low-power modes (including idle auto-gating, self-refresh, power-down, and power-down retention), low jitter with improved noise rejection, and configuration through APB/AHB/AXI register interfaces.
Beyond raw specs, Innosilicon says its IP is tracking toward mass production readiness. The company expects the first products using its LPDDR6/LPDDR5X technology to launch this year through multiple partners. It also claims to have developed a new framework that can cut product development cycles by around 30%, which could help device makers and chip designers bring new designs to market faster—especially important as memory demands rise across smartphones, tablets, laptops, and embedded systems.
If these early customer deliveries translate into shipping silicon on schedule, Innosilicon’s LPDDR6/LPDDR5X controller IP could become a notable option for companies looking to adopt faster LPDDR6-class memory performance while keeping power efficiency in focus.
